Search results for "Aviral Shrivastava"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava	Design of an RNS reverse converter for a new five-moduli special set.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek	Memory access optimization in compilation for coarse-grained reconfigurable architectures.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Jongeun Lee, Aviral Shrivastava	Static Analysis of Register File Vulnerability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho, Yunheung Paek	High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava	Fast and energy-efficient constant-coefficient FIR filters using residue number system.	ISLPED	2011	DBLP BibTeX RDF
1	Yooseong Kim, Aviral Shrivastava	CuMAPz: a tool to analyze memory access patterns in CUDA.	DAC	2011	DBLP DOI BibTeX RDF
1	Reiley Jeyapaul, Fei Hong, Abhishek Rhisheekesan, Aviral Shrivastava, Kyoungwoo Lee	UnSync: A Soft Error Resilient Redundant Multicore Architecture.	ICPP	2011	DBLP DOI BibTeX RDF	core-level redundancy, redundant architecture, hardware detection, low power, soft error, error resilient, multi-core architecture
1	Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula	Enabling Multithreading on CGRAs.	ICPP	2011	DBLP DOI BibTeX RDF	CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique
1	Ke Bai, Aviral Shrivastava, Saleel Kudchadker	Stack data management for Limited Local Memory (LLM) multi-core processors.	ASAP	2011	DBLP DOI BibTeX RDF
1	Reiley Jeyapaul, Aviral Shrivastava	Smart cache cleaning: energy efficient vulnerability reduction in embedded processors.	CASES	2011	DBLP DOI BibTeX RDF
1	Ke Bai, Di Lu, Aviral Shrivastava	Vector class on limited local memory (LLM) multi-core processors.	CASES	2011	DBLP DOI BibTeX RDF
1	Aarul Jain, Aviral Shrivastava, Chaitali Chakrabarti	LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Jing Lu, Yooseong Kim, Aviral Shrivastava, Chuan Huang	Branch penalty reduction on IBM cell SPUs via software branch hinting.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Reiley Jeyapaul, Aviral Shrivastava	Code Transformations for TLB Power Reduction.	International Journal of Parallel Programming	2010	DBLP DOI BibTeX RDF
1	Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian	Partitioning techniques for partially protected caches in resource-constrained embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Jongeun Lee, Aviral Shrivastava	A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Reiley Jeyapaul, Aviral Shrivastava	B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems.	SCOPES	2010	DBLP DOI BibTeX RDF
1	Seung Chul Jung, Aviral Shrivastava, Ke Bai	Dynamic code mapping for limited local memory systems.	ASAP	2010	DBLP DOI BibTeX RDF
1	Jeffrey Boyd, Hari Sundaram, Aviral Shrivastava	Power-accuracy tradeoffs in human activity transition detection.	DATE	2010	DBLP BibTeX RDF
1	Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Yunheung Paek	Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays.	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek	Operation and data mapping for CGRAs with multi-bank memory.	LCTES	2010	DBLP DOI BibTeX RDF	bank conflict, multi-bank memory, compilation, arbiter, coarse-grained reconfigurable architecture
1	Aviral Shrivastava, Jongeun Lee, Reiley Jeyapaul	Cache vulnerability equations for protecting data in embedded processor caches from soft errors.	LCTES	2010	DBLP DOI BibTeX RDF	cache vulnerability, static analysis, embedded processors, soft errors, code transformation, compiler technique
1	Tom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig	Compilation techniques for CGRAs: exploring all parallelization approaches.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Ke Bai, Aviral Shrivastava	Heap data management for limited local memory (LLM) multi-core processors.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Aviral Shrivastava, Arun Kannan, Jongeun Lee	A Software-Only Solution to Use Scratch Pads for Stack Data.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, Yunheung Paek	Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian	Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Yunheung Paek	A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak	Exploiting residue number system for power-efficient digital signal processing in embedded processors.	CASES	2009	DBLP DOI BibTeX RDF	compiler, power, processor, residue number system, per-
1	Arun Kannan, Aviral Shrivastava, Amit Pabalkar, Jongeun Lee	A software solution for dynamic stack management on scratch pad memory.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Jongeun Lee, Aviral Shrivastava	Compiler-managed register file protection for energy-efficient soft error reduction.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava	Code Transformations for TLB Power Reduction.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Jongeun Lee, Aviral Shrivastava	Static analysis to mitigate soft errors in register files.	DATE	2009	DBLP BibTeX RDF
1	Sai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava, Jongeun Lee, Tony Givargis	FSAF: File system aware flash translation layer for NAND Flash Memories.	DATE	2009	DBLP BibTeX RDF
1	Jongeun Lee, Aviral Shrivastava	A compiler optimization to reduce soft errors in register files.	LCTES	2009	DBLP DOI BibTeX RDF	architectural vulnerability factor, link-time optimization, embedded system, compilation, static analysis, soft error, register file
1	Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie	Register File Power Reduction Using Bypass Sensitive Compiler.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Amit Pabalkar, Aviral Shrivastava, Arun Kannan, Jongeun Lee	SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories.	HiPC	2008	DBLP DOI BibTeX RDF	Code overlay, Compilers, Scratchpad memory, Static code analysis
1	Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek	SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Aviral Shrivastava, Ilya Issenin, Nikil Dutt	A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi	PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Temperature and Process Variations Aware Power Gating of Functional Units.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Power Reduction of Functional Units Considering Temperature and Process Variations.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian	Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures.	DIPES	2008	DBLP DOI BibTeX RDF
1	Sanghyun Park, Aviral Shrivastava, Yunheung Paek	Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors.	DATE	2008	DBLP DOI BibTeX RDF
1	Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian	Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach.	ACM Multimedia	2008	DBLP DOI BibTeX RDF	error-awareness, cross-layer, soft error, video encoding
1	Jongeun Lee, Aviral Shrivastava	Static analysis of processor stall cycle aggregation.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	memory bound loops, processor free time, stall cycle aggregation, embedded systems, low power, code transformation
1	Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek	Automatic Design Space Exploration of Register Bypasses in Embedded Processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Satyajayant Misra, Guoliang Xue, Aviral Shrivastava	Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors.	ICC	2007	DBLP DOI BibTeX RDF
1	Qiang Zhu, Aviral Shrivastava, Nikil Dutt	Interactive presentation: Functional and timing validation of partially bypassed processor pipelines.	DATE	2007	DBLP DOI BibTeX RDF
1	Michael A. Baker, Aviral Shrivastava, Karam S. Chatha	Smart driver for power reduction in next generation bistable electrophoretic display technology.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	bistable display, display drivers, electrophoretic display, low power display
1	Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers
1	Prabhat Mishra, Aviral Shrivastava, Nikil Dutt	Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	programmable architecture, design space exploration, Architecture description language, embedded processor, retargetable compilation
1	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau	Retargetable pipeline hazard detection for partially bypassed processors.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian	Mitigating soft error failures for multimedia applications by selective data protection.	CASES	2006	DBLP DOI BibTeX RDF	horizontally partitioned caches, multimedia embedded systems, selective data protection, soft errors
1	Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek	Automatic generation of operation tables for fast exploration of bypasses in embedded processors.	DATE	2006	DBLP DOI BibTeX RDF
1	Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie	Bypass aware instruction scheduling for register file power reduction.	LCTES	2006	DBLP DOI BibTeX RDF	architecture-sensitive compiler, bypass-sensitive, forwarding paths, operation table, processor bypasses, reservation table, power consumption, register file
1	Aviral Shrivastava, Ilya Issenin, Nikil Dutt	Compilation techniques for energy reduction in horizontally partitioned cache architectures.	CASES	2005	DBLP DOI BibTeX RDF	XScale, horizontally-partitioned cache, mini-cache, split cache, compiler, energy, data cache
1	Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie	PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.	DATE	2005	DBLP DOI BibTeX RDF
1	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau	Aggregating processor free time for energy reduction.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	processor free time, embedded systems, aggregation, clock gating, code transformation, energy reduction
1	Aviral Shrivastava, Nikil D. Dutt	Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA).	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau	Operation tables for scheduling in the presence of incomplete bypassing.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	hazard detection, operation table, reservation table, scheduling, retargetable compilers, bypass
1	Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi	A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .	ISSS	2002	DBLP DOI BibTeX RDF	compressed instruction set, dual Instruction set, rISA, reduced bit-width instruction set, thumb, design space exploration, register pressure
1	Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau	An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.	DATE	2002	DBLP DOI BibTeX RDF
1	Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan	Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.	VLSI Design	2000	DBLP DOI BibTeX RDF

Publications of "Aviral Shrivastava" ( http://dblp.L3S.de/Authors/Aviral_Shrivastava )