| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Min Li, Azadeh Davoodi, Mohammad Tehranipoor |
A sensor-assisted self-authentication framework for hardware trojan detection.  |
DATE  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Min Li, Azadeh Davoodi, Lin Xie |
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth |
GRIP: Global Routing via Integer Programming. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Xie, Azadeh Davoodi |
Bound-Based Statistically-Critical Path Extraction Under Process Variations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tai-Hsuan Wu, Azadeh Davoodi, Jeff T. Linderoth |
Power-driven global routing for multi-supply voltage domains. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth |
Congestion analysis for global routing via integer programming. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Shojaei, Tai-Hsuan Wu, Azadeh Davoodi, Twan Basten |
A pareto-algebraic framework for signal power optimization in global routing. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
pareto algebra, global routing, dynamic power |
| 1 | Lin Xie, Azadeh Davoodi, Kewal K. Saluja |
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
post-silicon diagnosis, process variations |
| 1 | Lin Xie, Azadeh Davoodi |
Representative path selection for post-silicon timing prediction under variability. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
process variations, post-silicon validation |
| 1 | Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth |
A parallel integer programming approach to global routing. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
parallelism, integer programming, global routing |
| 1 | Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu |
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hamid Shojaei, Azadeh Davoodi |
Trace signal selection to enhance timing and logic visibility in post-silicon validation. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu |
Adjustment-Based Modeling for Timing Analysis Under Variability. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tai-Hsuan Wu, Azadeh Davoodi |
PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim |
Statistical static timing analysis considering leakage variability in power gated designs. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
process variations, leakage, power gating, ssta |
| 1 | Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth |
GRIP: scalable 3D global routing using integer programming. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
integer programming, global routing |
| 1 | Lin Xie, Azadeh Davoodi |
Bound-based identification of timing-violating paths under variability. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar |
False Path Aware Timing Yield Estimation under Variability. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi |
A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Xie, Azadeh Davoodi |
Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Ankur Srivastava |
Variability Driven Gate Sizing for Binning Yield Optimization. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Xie, Azadeh Davoodi |
Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Xie, Azadeh Davoodi |
Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Skew-Normal, process variation, Gaussian, statistical static timing analysis |
| 1 | Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi |
A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungseob Lee, Lin Xie, Azadeh Davoodi |
A Dual-Vt low leakage SRAM array robust to process variations. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu |
Adjustment-based modeling for statistical static timing analysis with high dimension of variability. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tai-Hsuan Wu, Azadeh Davoodi |
PaRS: fast and near-optimal grid-based cell sizing for library-based design. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi |
SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava |
Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jungseob Lee, Azadeh Davoodi |
Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak |
Statistical timing analysis using Kernel smoothing. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Wang, Matthew French, Azadeh Davoodi, Deepak Agarwal |
FPGA Dynamic Power Minimization through Placement and Routing Constraints. |
EURASIP J. Emb. Sys. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Ankur Srivastava |
Effective techniques for the generalized low-power binding problem. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Low-power binding, graph theory, high level synthesis |
| 1 | Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava |
Probabilistic Evaluation of Solutions in Variability-Driven Optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak |
A statistical methodology for wire-length prediction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Ankur Srivastava |
Probabilistic evaluation of solutions in variability-driven optimization. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
probabilistic optimization |
| 1 | Azadeh Davoodi, Ankur Srivastava |
Variability driven gate sizing for binning yield optimization. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
speed binning, process variations, gate sizing |
| 1 | Azadeh Davoodi, Ankur Srivastava |
Voltage scheduling under unpredictabilities: a risk management paradigm. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
design closure, voltage scheduling, low power, Predictability |
| 1 | Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava |
Simultaneous V/sub t/ selection and assignment for leakage optimization. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Ankur Srivastava |
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Ankur Srivastava |
Probabilistic dual-Vth leakage optimization under variability. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
optimization, process variations, leakage, automatic synthesis |
| 1 | Azadeh Davoodi, Ankur Srivastava |
Simultaneous floorplanning and resource binding: a probabilistic approach. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Ankur Srivastava |
Wake-up protocols for controlling current surges in MTCMOS-based technology. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Ankur Srivastava |
Variability-Driven Buffer Insertion Considering Correlations. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava |
Empirical models for net-length probability distribution and applications. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava |
High level techniques for power-grid noise immunity. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
high-level noise-immune optimization |
| 1 | Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava |
Variability inspired implementation selection problem. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava |
Efficient statistical timing analysis through error budgeting. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak |
Wire-length prediction using statistical techniques. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Azadeh Davoodi, Ankur Srivastava |
Effective graph theoretic techniques for the generalized low power binding problem. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
low-power binding, graph theory, high level synthesis |
| 1 | Azadeh Davoodi, Ankur Srivastava |
Voltage scheduling under unpredictabilities: a risk management paradigm. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
design closure, voltage scheduling, low power, predictability |
| 1 | Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava |
A Probabilistic Approach to Buffer Insertion. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
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