Search results for "B. Ramakrishna Rau"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien	Constructing and exploiting linear schedules with prescribed parallelism.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	multicluster VLIW, systolic array, Linear schedule
1	Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman	PICO: Automatically Designing Custom Computers.	IEEE Computer	2002	DBLP DOI BibTeX RDF
1	Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman	PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.	VLSI Signal Processing	2002	DBLP DOI BibTeX RDF	high-level hardware synthesis, automatic parallelization, datapath synthesis
1	B. Ramakrishna Rau, Michael S. Schlansker	Embedded Computer Architecture and Automation.	IEEE Computer	2001	DBLP DOI BibTeX RDF
1	Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau	Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	code size minimization, custom templates, instruction format design, noop compression, retargetable assembly, VLIW, design automation, EPIC
1	Michael S. Schlansker, B. Ramakrishna Rau	EPIC: Explicititly Parallel Instruction Computing.	IEEE Computer	2000	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, Michael S. Schlansker	Embedded Computing: New Directions in Architecture and Automation.	HiPC	2000	DBLP DOI BibTeX RDF
1	Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien	A Constructive Solution to the Juggling Problem in Processor Array Synthesis. (PDF / PS)	IPDPS	2000	DBLP DOI BibTeX RDF	Systolic array synthesis, Affine scheduling
1	Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider	High-Level Synthesis of Nonprogrammable Hardware Accelerators.	ASAP	2000	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau	The era of embedded computing.	CASES	2000	DBLP DOI BibTeX RDF
1	Santosh G. Abraham, B. Ramakrishna Rau	Efficient design space exploration in PICO.	CASES	2000	DBLP DOI BibTeX RDF	design space decomposition, hierarchical evaluation, multiple criteria optimization, multi-objective optimization, automated design
1	B. Ramakrishna Rau, Vinod Kathail, Shail Aditya	Machine-Description Driven Compilers for EPIC and VLIW Processors.	Design Autom. for Emb. Sys.	1999	DBLP DOI BibTeX RDF
1	Shail Aditya, B. Ramakrishna Rau, Vinod Kathail	Automatic Architectural Synthesis of VLIW and EPIC Processors. (PDF / PS)	ISSS	1999	DBLP DOI BibTeX RDF
1	John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau	Optimization of Machine Descriptions for Efficient Use.	International Journal of Parallel Programming	1998	DBLP DOI BibTeX RDF
1	Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau	Region-based compilation: Introduction, motivation, and initial experience.	International Journal of Parallel Programming	1997	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau	Iterative Modulo Scheduling.	International Journal of Parallel Programming	1996	DBLP BibTeX RDF
1	John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau	Optimization of Machine Descriptions for Efficient Use.	MICRO	1996	DBLP BibTeX RDF
1	Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker	Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.	MICRO	1996	DBLP BibTeX RDF	linear code regions, long-instruction-word machines, optimum scheduling, profile-driven instruction level parallel scheduling, profile-sensitive scheduler, ranking branch instructions, compiler optimization, scheduling heuristic, abstract model, optimising compilers, code scheduling
1	Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau	Region-based compilation: an introduction and motivation.	MICRO	1995	DBLP DOI BibTeX RDF	ILP compilation, code expansion, compilation time complexity, function inlining, region-based compilation
1	B. Ramakrishna Rau	Iterative modulo scheduling: an algorithm for software pipelining loops.	MICRO	1994	DBLP DOI BibTeX RDF	software pipelining, instruction scheduling, modulo scheduling, loop scheduling
1	B. Ramakrishna Rau, Joseph A. Fisher	Instruction-level parallel processing: History, overview, and perspective.	The Journal of Supercomputing	1993	DBLP DOI BibTeX RDF
1	Joseph A. Fisher, B. Ramakrishna Rau	Guest editors' introduction.	The Journal of Supercomputing	1993	DBLP DOI BibTeX RDF
1	Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
1	Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau	Reverse If-Conversion.	PLDI	1993	DBLP DOI BibTeX RDF
1	Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta	Predictability of load/store instruction latencies.	MICRO	1993	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau	Dynamically scheduled VLIW processors.	MICRO	1993	DBLP DOI BibTeX RDF	multiple operation issue, scoreboarding, dynamic scheduling, out-of-order execution, VLIW processors
1	B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker	Register Allocation for Software Pipelined Loops.	PLDI	1992	DBLP DOI BibTeX RDF
1	Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ASPLOS	1992	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai	Code generation schema for modulo scheduled loops.	MICRO	1992	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau	Pseudo-Randomly Interleaved Memory.	ISCA	1991	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau	Data Flow and Dependence Analysis for Instruction Level Parallelism.	LCPC	1991	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, David W. L. Yen, Wei C. Yen, Ross A. Towle	The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs.	IEEE Computer	1989	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen	The Cydram 5 Stride-Insensitive Memory System.	ICPP	1989	DBLP BibTeX RDF
1	B. Ramakrishna Rau	Cydra 5 Directed Dataflow Architecture.	COMPCON	1988	DBLP BibTeX RDF
1	B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard	Efficient code generation for horizontal architectures: Compiler techniques and architectural support.	ISCA	1982	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt	Architectural Support for the Efficient Generation of Code for Horizontal Architectures.	ASPLOS	1982	DBLP DOI BibTeX RDF
1	Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker	Systematically derived instruction sets for high-level language support.	ACM Southeast Regional Conference	1982	DBLP DOI BibTeX RDF	directly interpretable languages, space-time efficiency, syntax and semantics, compilation, interpretation, high-level languages, semantic gap, instruction set design
1	B. Ramakrishna Rau	Program Behavior and the Performance of Interleaved Memories.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau	Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	performance evaluation, multiprocessors, Analytical models, memory bandwidth, memory interference, interleaved memories
1	B. Ramakrishna Rau, George E. Rossman	The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units.	ISCA	1977	DBLP DOI BibTeX RDF
1	B. Ramakrishna Rau	A new philosophy for interconnection on multilayer boards.	DAC	1976	DBLP DOI BibTeX RDF

Publications of "B. Ramakrishna Rau" ( http://dblp.L3S.de/Authors/B._Ramakrishna_Rau )