Search results for "Baris Taskin"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jianchao Lu, Xiaomi Mao, Baris Taskin	Integrated Clock Mesh Synthesis With Incremental Register Placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Jianchao Lu, Ying Teng, Baris Taskin	A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Ying Teng, Baris Taskin	Synchronization scheme for brick-based rotary oscillator arrays.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Ankit More, Baris Taskin	3-D Parasitic Modeling for Rotary Interconnects.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Clock buffer polarity assignment with skew tuning.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Shannon M. Kurtas, Baris Taskin	Statistical Timing Analysis of the Clock Period Improvement through Clock Skew Scheduling.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Baris Taskin	CROA: Design and Analysis of the Custom Rotary Oscillatory Array.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Ying Teng, Baris Taskin	Process variation sensitivity of the Rotary Traveling Wave Oscillator.	ISQED	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Xiaomi Mao, Baris Taskin	Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis.	ISPD	2011	DBLP DOI BibTeX RDF
1	Ankit More, Baris Taskin	Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chip.	SLIP	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Vinayak Honkote, Xin Chen, Baris Taskin	Steiner tree based rotary clock routing with bounded skew and capacitive load balancing.	DATE	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Jianchao Lu, Yusuf Aksehir, Baris Taskin	Register On MEsh (ROME): A novel approach for clock mesh network synthesis.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Ying Teng, Jianchao Lu, Baris Taskin	ROA-brick topology for rotary resonant clocks.	ICCD	2011	DBLP DOI BibTeX RDF
1	Ankit More, Baris Taskin	EM and circuit co-simulation of a reconfigurable hybrid wireless NoC on 2D ICs.	ICCD	2011	DBLP DOI BibTeX RDF
1	Ying Teng, Baris Taskin	Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Post-CTS Delay Insertion.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Ankit More, Baris Taskin	Leakage current analysis for intra-chip wireless interconnects.	ISQED	2010	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Baris Taskin	Skew analysis and bounded skew constraint methodology for rotary clocking technology.	ISQED	2010	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Clock buffer polarity assignment considering capacitive load.	ISQED	2010	DBLP DOI BibTeX RDF
1	Ankit More, Baris Taskin	Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Jianchao Lu, Baris Taskin	Clock Tree Synthesis with XOR Gates for Polarity Assignment.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Baris Taskin	PEEC based parasitic modeling for power analysis on custom rotary rings.	ISLPED	2010	DBLP DOI BibTeX RDF	resonant clocking, simulation, modeling, interconnect
1	Ankit More, Baris Taskin	Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	on-chip antennas, VLSI, interconnects, electromagnetic
1	Ankit More, Baris Taskin	Simulation based study of wireless RF interconnects for practical CMOs implementation.	SLIP	2010	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Baris Taskin	Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array.	VLSI Design	2010	DBLP DOI BibTeX RDF	Resonant clocking, Capacitive load balancing, Optimization, Low power, Spice
1	Ankit More, Baris Taskin	Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC.	SoCC	2010	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Baris Taskin	Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array.	ICCD	2010	DBLP DOI BibTeX RDF
1	Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner	Custom topology rotary clock router with tree subnetworks.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Resonant rotary clocking, clock network design, multiphase synchronization, clock skew
1	Baris Taskin, Ivan S. Kourtev	Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits.	Journal of Circuits, Systems, and Computers	2009	DBLP DOI BibTeX RDF
1	Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo	A shift-register-based QCA memory architecture.	JETC	2009	DBLP DOI BibTeX RDF	clocking, Quantum-dot cellular automata, memory design
1	Vinayak Honkote, Baris Taskin	Zero clock skew synchronization with rotary clocking technology.	ISQED	2009	DBLP DOI BibTeX RDF
1	Vinayak Honkote, Baris Taskin	Custom rotary clock router.	ICCD	2008	DBLP DOI BibTeX RDF
1	Baris Taskin, Ivan S. Kourtev	Delay Insertion Method in Clock Skew Scheduling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Baris Taskin, Ivan S. Kourtev	Delay insertion method in clock skew scheduling.	ISPD	2005	DBLP DOI BibTeX RDF	delay insertion, re-convergent paths, optimization, linear programming, clock skew
1	Baris Taskin, Ivan S. Kourtev	Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Baris Taskin, Ivan S. Kourtev	Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits.	ISCAS	2004	DBLP BibTeX RDF
1	Baris Taskin, Ivan S. Kourtev	Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	optimization, linear programming, clock skew, cycle stealing

Publications of "Baris Taskin" ( http://dblp.L3S.de/Authors/Baris_Taskin )