Search results for "Benton H. Calhoun"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Benton H. Calhoun, John Lach, John A. Stankovic, David D. Wentzloff, Kamin Whitehouse, Adam T. Barth, Jonathan K. Brown, Qiang Li, Seunghyun Oh, Nathan E. Roberts, Yanqing Zhang	Body Sensor Networks: A Holistic Approach From Silicon to Users.	Proceedings of the IEEE	2012	DBLP DOI BibTeX RDF
1	Fan Zhang, Yanqing Zhang, Jason Silver, Yousef Shakhsheer, Manohar Nagaraju, Alicia Klinefelter, Jagdish Nayayan Pandey, James Boley, Eric J. Carlson, Aatmesh Shrivastava, Brian P. Otis, Benton H. Calhoun	A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Satyanand Nalam, Benton H. Calhoun	5T SRAM With Asymmetric Sizing for Improved Read Stability.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Jiajing Wang, Benton H. Calhoun	Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Jiajing Wang, A. Hoefler, Benton H. Calhoun	An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Randy W. Mann, Benton H. Calhoun	New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm.	ISQED	2011	DBLP DOI BibTeX RDF
1	Sudhanshu Khanna, Kyle Craig, Yousef Shakhsheer, Saad Arrabi, John Lach, Benton H. Calhoun	Stepped Supply Voltage Switching for energy constrained systems.	ISQED	2011	DBLP DOI BibTeX RDF
1	Joseph F. Ryan, Sudhanshu Khanna, Benton H. Calhoun	An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal.	ISLPED	2011	DBLP BibTeX RDF
1	Yousef Shakhsheer, Sudhanshu Khanna, Kyle Craig, Saad Arrabi, John Lach, Benton H. Calhoun	A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V.	CICC	2011	DBLP DOI BibTeX RDF
1	Brett H. Meyer, Benton H. Calhoun, John Lach, Kevin Skadron	Cost-effective safety and fault localization using distributed temporal redundancy.	CASES	2011	DBLP DOI BibTeX RDF
1	Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun	Dynamic write limited minimum operating voltage for nanoscale SRAMs.	DATE	2011	DBLP DOI BibTeX RDF
1	Brett H. Meyer, Nishant J. George, Benton H. Calhoun, John Lach, Kevin Skadron	Reducing the cost of redundant execution in safety-critical systems using relaxed dedication.	DATE	2011	DBLP DOI BibTeX RDF
1	Benton H. Calhoun, D. Brooks	Can Subthreshold and Near-Threshold Circuits Go Mainstream?	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun	Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Stuart N. Wooters, Benton H. Calhoun, Travis N. Blalock	An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Randy W. Mann, Satyanand Nalam, Jiajing Wang, Benton H. Calhoun	Limits of bias based assist methods in nano-scale 6T SRAM.	ISQED	2010	DBLP DOI BibTeX RDF
1	Satyanand Nalam, Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken, Benton H. Calhoun	Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation.	ISQED	2010	DBLP DOI BibTeX RDF
1	Joseph F. Ryan, Benton H. Calhoun	A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun	Improving SRAM Vmin and yield by using variation-aware BTI stress.	CICC	2010	DBLP DOI BibTeX RDF
1	Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun	Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.	DAC	2010	DBLP DOI BibTeX RDF	optimization, design space exploration, SRAM, virtual prototype, iterative design
1	Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan	SRAM-based NBTI/PBTI sensor system design.	DAC	2010	DBLP DOI BibTeX RDF	PBTI, sensor system design, sensor, redundancy, process variation, aging, yield, SRAM, NBTI
1	Benton H. Calhoun, Sudhanshu Khanna, Yanqing Zhang, Joseph F. Ryan, Brian P. Otis	System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Mark A. Hanson, Harry C. Powell Jr., Adam T. Barth, Kyle Ringgenberg, Benton H. Calhoun, James H. Aylor, John Lach	Body Area Sensor Networks: Challenges and Opportunities.	IEEE Computer	2009	DBLP DOI BibTeX RDF
1	Sudhanshu Khanna, Benton H. Calhoun	Serial sub-threshold circuits for ultra-low-power systems.	ISLPED	2009	DBLP DOI BibTeX RDF	bit width, serial systems, leakage, ultra low power, sub-threshold
1	Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun	A 2.6 µW sub-threshold mixed-signal ECG SoC.	ISLPED	2009	DBLP DOI BibTeX RDF	sub-threshold SoC, sub-threshold operation, system on chip, electrocardiogram
1	Satyanand Nalam, Benton H. Calhoun	Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T.	CICC	2009	DBLP DOI BibTeX RDF
1	Benton H. Calhoun, Sudhanshu Khanna, Randy W. Mann, Jiajing Wang	Sub-threshold Circuit Design with Shrinking CMOS Devices.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Benton H. Calhoun, Jonathan F. Bolus, Sudhanshu Khanna, Andrew D. Jurik, Alfred C. Weaver, Travis N. Blalock	Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun	A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.	ICCD	2009	DBLP DOI BibTeX RDF
1	Mateja Putic, Liang Di, Benton H. Calhoun, John Lach	Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design.	ICCD	2009	DBLP DOI BibTeX RDF
1	Joseph F. Ryan, Benton H. Calhoun	Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.	ISQED	2008	DBLP DOI BibTeX RDF	Sub-threshold Circuits, Sub-Vt, Sense-Amplifiers, Variation, Offset
1	Jiajing Wang, Satyanand Nalam, Benton H. Calhoun	Analyzing static and dynamic write margin for nanometer SRAMs.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar	Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Liang Di, Mateja Putic, John Lach, Benton H. Calhoun	Power switch characterization for fine-grained dynamic voltage scaling.	ICCD	2008	DBLP DOI BibTeX RDF
1	Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun	Analyzing and modeling process balance for sub-threshold circuit design.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	minimum energy operation, process balance, process imbalance, sub-threshold digital circuits, sub-threshold modeling
1	Benton H. Calhoun, Alice Wang, Naveen Verma, Anantha Chandrakasan	Sub-threshold design: the challenges of minimizing circuit energy.	ISLPED	2006	DBLP DOI BibTeX RDF	low voltage memory, sub-threshold digital circuits, sub-threshold logic, process variations, dynamic voltage scaling
1	Benton H. Calhoun, Denis C. Daly, Naveen Verma, Daniel F. Finchelstein, David D. Wentzloff, Alice Wang, Seong-Hwan Cho, Anantha P. Chandrakasan	Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	wireless sensor networks, low-power design, Integrated circuits, energy-aware systems
1	Eugene Shih, Seong-Hwan Cho, Fred S. Lee, Benton H. Calhoun, Anantha Chandrakasan	Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	short-range radio design, wireless sensor networks, energy-efficiency, power-aware
1	Benton H. Calhoun, Anantha Chandrakasan	Characterizing and modeling minimum energy operation for subthreshold circuits.	ISLPED	2004	DBLP DOI BibTeX RDF	minimum energy point, subthreshold model, energy model, subthreshold circuits
1	David D. Wentzloff, Benton H. Calhoun, Rex Min, Alice Wang, Nathan Ickes, Anantha Chandrakasan	Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Benton H. Calhoun, Frank Honoré, Anantha Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
1	Frank Honoré, Benton H. Calhoun, Anantha Chandrakasan	Power-aware architectures and circuits for FPGA-based signal processing.	FPGA	2003	DBLP DOI BibTeX RDF

Publications of "Benton H. Calhoun" ( http://dblp.L3S.de/Authors/Benton_H._Calhoun )