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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18 occurrences of 18 keywords
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Results
Found 40 publication records. Showing 40 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Nandish Ashutosh Mehta, Bharadwaj Amrutur |
Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Pramod, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy |
CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy.  |
VLSI Design  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Aparna Mandke Dani, Bharadwaj Amrutur, Y. N. Srikant, Chiranjib Bhattacharyya |
TCP: Thread Contention Predictor for Parallel Programs.  |
PDP  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bharadwaj Amrutur, Pratap Kumar Das, Rajath Vasudevamurthy |
0.84 ps Resolution Clock Skew Measurement via Subsampling.  |
IEEE Trans. VLSI Syst.  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi |
Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding.  |
IEEE Trans. Circuits Syst. Video Techn.  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aparna Mandke Dani, Bharadwaj Amrutur, Y. N. Srikant |
Applying genetic algorithms to optimize the power in tiled SNUCA chip multicore architectures.  |
SAC  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Vikram Chaturvedi, Bharadwaj Amrutur |
A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS Technology.  |
VLSI Design  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Satyam Dwivedi, Bharadwaj Amrutur, Navakanta Bhat |
Power Scalable Digital Baseband Architecture for IEEE 802.15.4.  |
VLSI Design  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Siva Rama Krishna V., Bharadwaj Amrutur, Navakanta Bhat, Chakra Pani K., Sampath Srinivasan |
Detection of Glycated Hemoglobin using 3-Aminophenylboronic Acid Modified Graphene Oxide.  |
BIODEVICES  |
2011 |
DBLP BibTeX RDF |
|
| 1 | Rajath Vasudevamurthy, Pratap Kumar Das, Bharadwaj Amrutur |
A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test.  |
ISCAS  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Ghosal, S. A. Kannan, Bharadwaj Amrutur |
A power scalable receiver front-end at 2.4 GHz.  |
ISCAS  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur |
Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique.  |
IEEE Trans. VLSI Syst.  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan |
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Aparna Mandke Dani, Keshavan Varadarajan, Bharadwaj Amrutur, Y. N. Srikant |
Accelerating multi-core simulators.  |
SAC  |
2010 |
DBLP DOI BibTeX RDF |
chip multi-core, multi-core platform, timed petri-nets, instruction set simulator, cache simulator |
| 1 | M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji |
False Error Vulnerability Study of On-line Soft Error Detection Mechanisms.  |
J. Electronic Testing  |
2010 |
DBLP BibTeX RDF |
|
| 1 | Nandish Ashutosh Mehta, Gururaj V. Naik, Bharadwaj S. Amrutur |
In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits.  |
ISLPED  |
2010 |
DBLP DOI BibTeX RDF |
DVTS loop, in-situ power monitor, power optimum point, variable body bias, variable supply voltage, low power, ground bounce |
| 1 | Ajit Gupte, Bharadwaj Amrutur |
Adaptive Global Elimination Algorithm for Low Power Motion Estimation (J. Low Power Electronics 5: 1-16 (2009)).  |
J. Low Power Electronics  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Sreejith, Bharadwaj Amrutur, Ashok Balivada |
A Workload Based Lookup Table for Minimal Power Operation Under Supply and Body Bias Control.  |
J. Low Power Electronics  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajit Gupte, Bharadwaj Amrutur |
Adaptive Global Elimination Algorithm for Low Power Motion Estimation.  |
J. Low Power Electronics  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur |
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration.  |
VLSI Design  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan |
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks.  |
J. Low Power Electronics  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Arvind Madan, Bharadwaj Amrutur |
Power reduction in on-chip interconnection network by serialization.  |
ISLPED  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajit Gupte, Bharadwaj Amrutur |
An adaptive, feature-based low power motion estimation algorithm.  |
ICME  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur |
Energy Reduction in SRAM using Dynamic Voltage and Frequency Management.  |
VLSI Design  |
2008 |
DBLP DOI BibTeX RDF |
Delay Monitor, DVFM, Pareto optimal curve, Replica circuits, SRAM, Energy reduction, Energy monitor |
| 1 | Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind |
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.  |
VLSI Design  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur |
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization.  |
VLSI Design  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jagdish Nayayan Pandey, Bharadwaj Amrutur, Sudhir S. Kudva |
Quadrature generation techniques for frequency multiplication based oscillators.  |
ISCAS  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat |
Optimal power and noise allocation for analog and digital sections of a low power radio receiver.  |
ISLPED  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur |
A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read.  |
VLSI Design  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur |
Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block.  |
VLSI Design  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji |
False Error Study of On-line Soft Error Detection Mechanisms.  |
IOLTS  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Rajan, Ramaswamy Govindarajan, Bharadwaj Amrutur |
Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses.  |
PACT  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | R. G. Raghavendra, Bharadwaj Amrutur |
Area efficient loop filter design for charge pump phase locked loop.  |
ACM Great Lakes Symposium on VLSI  |
2007 |
DBLP DOI BibTeX RDF |
dual-path loop filter |
| 1 | Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant |
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations.  |
CASES  |
2007 |
DBLP DOI BibTeX RDF |
interconnect, energy modeling, energy-aware scheduling, clustered VLIW processors |
| 1 | U. K. Vijay, Bharadwaj Amrutur |
Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture.  |
VLSI Design  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur |
A Low Power Frequency Multiplication Technique for ZigBee Transciever.  |
VLSI Design  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | K. R. Viveka, Abhilasha Kawle, Bharadwaj Amrutur |
Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique.  |
VLSI Design  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji |
Modified Stability Checking for On-line Error Detection.  |
VLSI Design  |
2007 |
DBLP DOI BibTeX RDF |
crosstalk faults and transient faults, SEU testing, modified stability checking, delay faults, self-checking circuits, Concurrent testing, on-line error detection |
| 1 | Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell |
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions.  |
MICRO  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan |
A scalable low power issue queue for large instruction window processors.  |
ICS  |
2006 |
DBLP DOI BibTeX RDF |
complexity-effective architecture, wakeup logic, low-power architecture, issue logic |
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