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Publications of "Biman Chattopadhyay" ( http://dblp.L3S.de/Authors/Biman_Chattopadhyay )

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Publication years (Num. hits)
2009 (1) 2010 (1) 2011 (2)
Publication types (Num. hits)
inproceedings(4)
Venues (Conferences, Journals, ...)
CICC(2) ISCAS(1) VLSI Design(1)
Authors
Anant S. Kamath(4) Biman Chattopadhyay(4) Gopalkrishna Nayak(2) Karthik Subburaj(1) Satyasai Evani(1)
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Found 4 publication records. Showing 4 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS. Search on Bibsonomy CICC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak A 1.8GHz Digital PLL in 65nm CMOS. Search on Bibsonomy VLSI Design The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Anant S. Kamath, Biman Chattopadhyay A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Anant S. Kamath, Biman Chattopadhyay, Gopalkrishna Nayak A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0. Search on Bibsonomy CICC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
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