| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Li-Chuan Chang, Chih-Hung Kuo, Bin-Da Liu |
A Two-Stage Rate Control Mechanism for RDO-Based H.264/AVC Encoders.  |
IEEE Trans. Circuits Syst. Video Techn.  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Tse Wei, Chia-Wei Tien, Bin-Da Liu, Jar-Ferr Yang |
Adaptive Truncation Algorithm for Hadamard-Transformed H.264/AVC Lossless Video Coding. |
IEEE Trans. Circuits Syst. Video Techn. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuan-Ta Hsieh, Bin-Da Liu, Jian-Fu Wu, Chiao-Li Fang, Hann-Huei Tsai, Ying-Zong Juang |
A High Current Accuracy Boost White LED Driver Based on Offset Calibration Technique. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsieh-Wei Lee, King-Chu Hung, Bin-Da Liu, Sheau-Fang Lei, Hsin-Wen Ting |
Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Karunanithi Bharanitharan, Bin-Da Liu, Jar-Ferr Yang |
Classified Region Algorithm for Fast Intermode Decision in H.264/AVC Encoder. |
EURASIP J. Adv. Sig. Proc. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Heng-Yao Lin, Kuan-Hsien Wu, Bin-Da Liu, Jar-Ferr Yang |
An Efficient VLSI Architecture for Transform-Based Intra Prediction in H.264/AVC. |
IEEE Trans. Circuits Syst. Video Techn. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Hung Kuo, Li-Chuan Chang, Kuan-Wei Fan, Bin-Da Liu |
Hardware/Software Codesign of a Low-Cost Rate Control Scheme for H.264/AVC. |
IEEE Trans. Circuits Syst. Video Techn. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Li-Chuan Chang, Chih-Hung Kuo, Bin-Da Liu |
Low complexity MAD prediction algorithms for rate controllable H.264/AVC hardware encoders. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chih Chao, Shih-Tse Wei, Bin-Da Liu, Jar-Ferr Yang |
Combined CAVLC Decoder, Inverse Quantizer, and Transform Kernel in Compact H.264/AVC Decoder. |
IEEE Trans. Circuits Syst. Video Techn. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwei Zhang, Ming-Yan Yu, Bin-Da Liu, Xiao-Feng Huang |
A High-Speed and EDP-Efficient Range-Matching Scheme for Packet Classification. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Tse Wei, Shang-Ru Shen, Bin-Da Liu, Jar-Ferr Yang |
Lossless image and video coding based on H.264/AVC intra predictions with simplified interpolations. |
ICIP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwei Zhang, Yizheng Ye, Bin-Da Liu, Feng Guan |
Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Wei Tien, Heng-Yao Lin, Bin-Da Liu, Jar-Ferr Yang |
Transform-domain Partial Prediction Algorithm for Intra Prediction in H.264/AVC. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Chi Chang, Kai-Hui Chen, Tsorng-Juu Liang, Bin-Da Liu |
Design of One-cycle Control Power Factor Correction IC with Unipolar Supply Voltage. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Chien-Hung Tsai, Bin-Da Liu, Soon-Jyh Chang |
A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsin-Hung Ou, Soon-Jyh Chang, Bin-Da Liu |
Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsin-Hung Ou, Bin-Da Liu, Soon-Jyh Chang |
A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang |
A Histogram-Based Testing Method for Estimating A/D Converter Performance. |
IEEE T. Instrumentation and Measurement |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang |
A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder. |
IEEE Transactions on Multimedia |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | K. Bharanitharan, Bin-Da Liu, Jar-Ferr Yang, Wen-Chih Tsai |
A Low Complexity Detection of Discrete Cross Differences for Fast H.264/AVC Intra Prediction. |
IEEE Transactions on Multimedia |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwei Zhang, Yizheng Ye, Bin-Da Liu |
A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chih Chao, Kuan-Hung Lin, Bin-Da Liu, Jar-Ferr Yang |
An approximate square criterion for H.264/AVC intra mode decision. |
ICME |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Hung Kuo, Li-Chuan Chang, Zheng-Wei Liu, Bin-Da Liu |
System level design of a spatio-temporal video resampling architecture. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang |
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. |
J. Electronic Testing |
2007 |
DBLP DOI BibTeX RDF |
Reconfigurable oscillator, Sinusoidal signal generator, Sigma-delta modulator |
| 1 | Yi-Chih Chao, Hui-Hsien Tsai, Yu-Hsiu Lin, Jar-Ferr Yang, Bin-Da Liu |
A Novel Design for Computation of All Transforms in H.264/AVC Decoders. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Li-Chuan Chang, Yen-Sung Chen, Rung-Wen Liou, Chih-Hung Kuo, Chia-Hung Yeh, Bin-Da Liu |
A Real Time and Low Cost Hardware Architecture for Video Abstraction System. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu |
Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwei Zhang, Yizheng Ye, Bin-Da Liu |
A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
mismatch-dependent, voltage detecting, low power, high speed, CAM |
| 1 | Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu |
A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chih Chao, Ji-Kun Lin, Jar-Ferr Yang, Bin-Da Liu |
A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu |
Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang |
An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianwei Zhang, Yizheng Ye, Bin-Da Liu |
A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Heng-Yao Lin, Jwu-Jin Yang, Bin-Da Liu, Jar-Ferr Yang |
Efficient deblocking filter architecture for H.264 video coders. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang |
Low power design of H.264 CAVLC decoder. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Huang Lin, Bin-Da Liu |
A gray system modeling approach to the prediction of calibration intervals. |
IEEE T. Instrumentation and Measurement |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Bin Wu, C.-Y. Yao, Bin-Da Liu, Jar-Ferr Yang |
DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation. |
IEEE Trans. Circuits Syst. Video Techn. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsin-Hung Ou, Bin-Da Liu |
A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Heng-Yao Lin, Yi-Chih Chao, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang |
Combined 2-D transform and quantization architectures for H.264 video coders. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Bin Lin, Bin-Da Liu |
Coefficients Generation for the 4th-Order Leapfrog Sigma-Delta A/D Converters. |
IEICE Transactions |
2004 |
DBLP BibTeX RDF |
|
| 1 | Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang, Jiun-Lung Wang |
Efficient recursive structures for forward and inverse discrete cosine transform. |
IEEE Transactions on Signal Processing |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu |
A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
CMOS analog circuit, flash analog-to-digital converter, rail-to-rail, low power, comparator |
| 1 | Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang |
A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhan-Yuan Cheng, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang |
Unified selectable fixed-coefficient recursive structures for computing DCT, IMDCT and subband synthesis filtering. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang |
Condensed recursive structures for computing multi-dimensional DCT with arbitrary length. |
ISCAS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang |
A fuzzy-based impulse noise detection and cancellation for real-time processing in video receivers. |
IEEE T. Instrumentation and Measurement |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang |
Adaptive postprocessors with DCT-based block classifications. |
IEEE Trans. Circuits Syst. Video Techn. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu |
Low-power and low-voltage fully parallel content-addressable memory. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang |
Direct recursive structures for computing radix-r two-dimensional DCT. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Bin Lin, Bin-Da Liu |
The high-resolution multi-tone signal generators. |
APCCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi-Sheng Lin, Bin-Da Liu |
Design of a pipelined and expandable sorting architecture with simple control scheme. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Shin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu |
A scalable sorting architecture based on maskable WTA/MAX circuit. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Bin-Da Liu, Chuen-Yau Chen, Ju-Ying Tsao |
Design of adaptive fuzzy logic controller based on linguistic-hedge concepts and genetic algorithms. |
IEEE Transactions on Systems, Man, and Cybernetics, Part B |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu |
A hardware design approach for merge-sorting network. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang |
Adaptive postprocessors with DCT-based block classifications. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chien-Cheng Yu, Wei-Ping Wang, Bin-Da Liu |
A new level converter for low-power applications. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu |
A graph representation for programmable logic arrays to facilitate testing and logic design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Bin-Da Liu, Chun-Yueh Huang |
Design and implementation of the tree-based fuzzy logic controller. |
IEEE Transactions on Systems, Man, and Cybernetics, Part B |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chang Hsia, Jar-Ferr Yang, Bin-Da Liu |
Efficient postprocessor for blocky effect removal based on transform characteristics. |
IEEE Trans. Circuits Syst. Video Techn. |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu |
A practical current sensing technique for IDDQ testing. |
IEEE Trans. VLSI Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang |
Performance-directed compaction for VLSI symbolic layouts. |
Computer-Aided Design |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee |
An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Bin-Da Liu, Chun-Yueh Huang |
Array Based Fuzzy Inference Mechanism Implemented with Current-Mode CMOS Circuits. |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu |
Functional Text Pattern Generation for Asynchronous Circuits. |
ISCAS |
1993 |
DBLP BibTeX RDF |
|
| 1 | Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang |
Layout Compaction with Minimzed Delay Bound on Timing Critical Paths. |
ISCAS |
1993 |
DBLP BibTeX RDF |
|
| 1 | Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang |
A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths. |
ICCAD |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Pao-Chuan Chen, Bin-Da Liu, Jhing-Fa Wang |
Overall consideration of scan design and test generation. |
ICCAD |
1992 |
DBLP DOI BibTeX RDF |
|
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