Search results for "Bingfeng Mei"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Bjorn De Sutter, Osman Allam, Praveen Raghavan, Roeland Vandebriel, Hans Cappelle, Tom Vander Aa, Bingfeng Mei	An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Mladen Berekovic, Andreas Kanstein, Bingfeng Mei, Bjorn De Sutter	Mapping of nomadic multimedia applications on the ADRES reconfigurable array processor.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest	Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont	Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	H.264/AVC decoder, FPGA, multimedia, embedded system, reconfigurable architecture, VLIW
1	Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei	Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays.	LCTES	2008	DBLP DOI BibTeX RDF	register allocation, placement and routing, coarse-grained, reconfigurable arrays
1	Tom Vander Aa, Bingfeng Mei, Bjorn De Sutter	A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots.	CASES	2007	DBLP DOI BibTeX RDF	VLIW scheduling, code hoisting, predication
1	Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Sukjin Kim	Hardware and a Tool Chain for ADRES.	ARC	2006	DBLP DOI BibTeX RDF
1	Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins	Architecture Exploration for a Reconfigurable Architecture Template.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF
1	Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei	Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes.	FPL	2005	DBLP BibTeX RDF
1	Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein	Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.	FPL	2005	DBLP BibTeX RDF
1	Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll	Design Style Case Study for Embedded Multi Media Compute Nodes.	RTSS	2004	DBLP DOI BibTeX RDF
1	Bingfeng Mei, Serge Vernalde, Diederik Verkest, Rudy Lauwereins	Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study.	DATE	2004	DBLP DOI BibTeX RDF
1	Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins	ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.	FPL	2003	DBLP DOI BibTeX RDF
1	Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins	Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling.	DATE	2003	DBLP DOI BibTeX RDF
1	Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man	Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.	FPL	2001	DBLP DOI BibTeX RDF

Publications of "Bingfeng Mei" ( http://dblp.L3S.de/Authors/Bingfeng_Mei )