Search results for "Bipul Chandra Paul"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Bipul C. Paul, Krishnendu Chakrabarty	Advances in nanoelectronics circuits and systems [Editorial].	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra	Optimized Circuit Failure Prediction for Aging: Practicality and Promise.	ITC	2008	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima	ROM based logic (RBL) design: High-performance and low-power adders.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Prospect of ballistic CNFET in high performance applications: Modeling and analysis.	JETC	2007	DBLP DOI BibTeX RDF	Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
1	Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra	Circuit Failure Prediction and Its Application to Transistor Aging.	VTS	2007	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy	Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Bipul C. Paul, Kaushik Roy	Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Process variation, spatial correlation, statistical timing analysis
1	Bipul C. Paul, Kaushik Roy	Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	adaptive body bias design, statistical analysis, process variation, delay fault testing
1	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Modeling and analysis of circuit performance of ballistic CNFET.	DAC	2006	DBLP DOI BibTeX RDF	ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance
1	Aditya Bansal, Bipul Chandra Paul, Kaushik Roy	An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Amit Agarwal, Kaushik Roy	Low-power design techniques for scaled technologies.	Integration	2006	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy	Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.	DATE	2006	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.	DATE	2006	DBLP DOI BibTeX RDF
1	Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy	A process-tolerant cache architecture for improved yield in nanoscale technologies.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy	Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy	Statistical Timing Analysis using Levelized Covariance Propagation.	DATE	2005	DBLP DOI BibTeX RDF
1	Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy	Enhancing Yield at the End of the Technology Roadmap.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Cassondra Neau, Kaushik Roy	Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.	ITC	2004	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy	Device optimization for ultra-low power digital sub-threshold operation.	ISLPED	2004	DBLP DOI BibTeX RDF	device optimization, sub-threshold operation, ultra-low power applications
1	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy	Novel sizing algorithm for yield improvement under process variation in nanometer technology.	DAC	2004	DBLP DOI BibTeX RDF	Performance, Design, Algorithms, Reliability
1	Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy	Adaptive supply voltage technique for low swing interconnects.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Amit Agarwal, Bipul Chandra Paul, Kaushik Roy	A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.	IOLTS	2004	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Kaushik Roy	Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.	ITC	2002	DBLP DOI BibTeX RDF
1	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy	Dynamic Noise Analysis with Capacitive and Inductive Coupling.	VLSI Design	2002	DBLP DOI BibTeX RDF	capacitiance, dynamic noise margin, crosstalk, inductance, noise analysis, deep submicron, noise model
1	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul	Robust subthreshold logic for ultra-low power operation.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy	Design Verification and Robust Design Technique for Cross-Talk Faults.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul	Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul	Robust ultra-low power sub-threshold DTMOS logic.	ISLPED	2000	DBLP DOI BibTeX RDF

Publications of Bipul Chandra Paul Bipul C. Paul ( http://dblp.L3S.de/Authors/Bipul_Chandra_Paul )