Search results for "Bluespec"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Teemu Pitkänen, Vesa-Matti Hartikainen, Nirav Dave, Gopal Raghavan	802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec.	SAMOS	2008	DBLP DOI BibTeX RDF
2	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
2	Ravi Nanavati	Experience report: a pure shirt fits.	ICFP	2008	DBLP DOI BibTeX RDF	functional programming, Haskell, monads, Bluespec
2	Gaurav Singh, Sandeep K. Shukla	Verifying Compiler Based Refinement of BluespecTM.	SPIN	2008	DBLP DOI BibTeX RDF	Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker
2	Flavius Gruian, Mark Westmijze	BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management.	SYNASC	2007	DBLP DOI BibTeX RDF
2	Hiren D. Patel, Sandeep K. Shukla	Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL.	DATE	2007	DBLP DOI BibTeX RDF
2	Gaurav Singh, Sandeep K. Shukla	Model Checking Bluespec Specified Hardware Designs.	MTV	2007	DBLP DOI BibTeX RDF
2	Flavius Gruian, Mark Westmijze	BlueJEP: a flexible and high-performance Java embedded processor.	JTRES	2007	DBLP DOI BibTeX RDF	embedded systems, Java processor, Bluespec
2	Nirav Dave, Man Cheuk Ng, Arvind	Automatic synthesis of cache-coherence protocol processors using Bluespec.	MEMOCODE	2005	DBLP DOI BibTeX RDF
2	Rishiyur S. Nikhil	Bluespec System Verilog: efficient, correct RTL from high level specifications.	MEMOCODE	2004	DBLP DOI BibTeX RDF
2	Nirav Dave	Designing a reorder buffer in Bluespec.	MEMOCODE	2004	DBLP DOI BibTeX RDF
2	Arvind	Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk.	MEMOCODE	2003	DBLP DOI BibTeX RDF
1	Dominic Richards, David R. Lester	A monadic approach to automated reasoning for Bluespec SystemVerilog.	ISSE	2011	DBLP DOI BibTeX RDF
1	Mohammed M. Farag, Lee W. Lerner, Cameron D. Patterson	Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement.	FPL	2011	DBLP DOI BibTeX RDF	software attacks, Tailored Trustworthy Space, security, formal verification, cognitive radio, reconfigurable hardware, data-intensive computing, Bluespec
1	Jirí Simsa, Satnam Singh	Designing hardware with dynamic memory abstraction.	FPGA	2010	DBLP DOI BibTeX RDF	c to gates, high-level synthesis, parallel execution, dynamic memory, bluespec
1	Flavius Gruian, Mark Westmijze	Investigating hardware micro-instruction folding in a Java embedded processor.	JTRES	2010	DBLP DOI BibTeX RDF	BlueJEP, bytecode folding, embedded systems, Java processors, Bluespec
1	Daniel Gajski, Todd M. Austin, Steve Svoboda	What input-language is the best choice for high level synthesis (HLS)?	DAC	2010	DBLP DOI BibTeX RDF
1	Rishiyur S. Nikhil	Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design).	GPCE	2009	DBLP DOI BibTeX RDF	bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing
1	Edgar G. Daylight, Sandeep K. Shukla	On the Difficulties of Concurrent-System Design, Illustrated with a 2×2 Switch Case Study.	FM	2009	DBLP DOI BibTeX RDF	adaptability, non-functional requirements, formal specification languages, local reasoning
1	Arvind, Rishiyur S. Nikhil	Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract).	MEMOCODE	2008	DBLP DOI BibTeX RDF
1	Michal Karczmarek, Arvind	Synthesis from multi-cycle atomic actions as a solution to the timing closure problem.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Kermin Fleming, Chun-Chieh Lin, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks	H.264 Decoder: A Case Study in Multiple Design Points.	MEMOCODE	2008	DBLP DOI BibTeX RDF
1	Hiren D. Patel, Sandeep K. Shukla	On Cosimulating Multiple Abstraction-Level System-Level Models.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Jae W. Lee, Myron King, Krste Asanovic	Continual hashing for efficient fine-grain state inconsistency detection.	ICCD	2007	DBLP DOI BibTeX RDF
1	Nirav Dave, Arvind, Michael Pellauer	Scheduling as Rule Composition.	MEMOCODE	2007	DBLP DOI BibTeX RDF
1	Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks	From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols.	MEMOCODE	2007	DBLP DOI BibTeX RDF
1	Hiren D. Patel, Sandeep K. Shukla, E. Mednick, Rishiyur S. Nikhil	A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design.	MEMOCODE	2006	DBLP DOI BibTeX RDF
1	Nirav Dave, Michael Pellauer, S. Gerding, Arvind	802.11a transmitter: a case study in microarchitectural exploration.	MEMOCODE	2006	DBLP DOI BibTeX RDF
1	Gaurav Singh, Sandeep K. Shukla	Low-power hardware synthesis from TRS-based specifications.	MEMOCODE	2006	DBLP DOI BibTeX RDF
1	Ritwik Bhattacharya, Steven M. German, Ganesh Gopalakrishnan	Exploiting Symmetry and Transactions for Partial Order Reduction of Rule Based Specifications.	SPIN	2006	DBLP DOI BibTeX RDF
1	Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil	Synthesis of synchronous assertions with guarded atomic actions.	MEMOCODE	2005	DBLP DOI BibTeX RDF
1	Roland E. Wunderlich, James C. Hoe	In-system FPGA prototyping of an itanium microarchitecture.	FPGA	2004	DBLP DOI BibTeX RDF
1	Roland E. Wunderlich, James C. Hoe	In-System FPGA Prototyping of an Itanium Microarchitecture.	ICCD	2004	DBLP DOI BibTeX RDF