Search results for "Bo Yao"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Bo Yao, Pascal Belin, Christoph Scheepers	Brain 'talks over' boring quotes: Top-down activation of voice-selective areas while listening to monotonous direct speech quotations.	NeuroImage	2012	DBLP DOI BibTeX RDF
1	Bo Yao, Pascal Belin, Christoph Scheepers	Silent Reading of Direct versus Indirect Speech Activates Voice-selective Areas in the Auditory Cortex.	J. Cognitive Neuroscience	2011	DBLP DOI BibTeX RDF
1	Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng	On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Shide Liang, Dandan Zheng, Daron M. Standley, Bo Yao, Martin Zacharias, Chi Zhang	EPSVR and EPMeta: prediction of antigenic epitopes using support vector regression and multiple server results.	BMC Bioinformatics	2010	DBLP DOI BibTeX RDF
1	Bo Yao, Irith Pomeranz, Sudhakar M. Reddy	Deterministic broadside test generation for transition path delay faults.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	broadside test, deterministic test generation, path delay fault, transition fault
1	Weihua Zeng, Bo Yao, Tao Wang, Hengchen Liu	Research on ANN-based model of joint collocation of water quantity and quality.	ICNC	2010	DBLP DOI BibTeX RDF
1	Bo Yao, Lei Huang, Changping Liu	Adaptive Defogging of a Single Image.	ISCID	2009	DBLP DOI BibTeX RDF
1	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng	Efficient Timing Analysis With Known False Paths Using Biclique Covering.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng	Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.	ISQED	2007	DBLP DOI BibTeX RDF
1	Bo Yao, Qingchun Chen	On the Temporal-Spatial Correlation Based Fault-Tolerant Dynamic Event Region Detection Scheme in Wireless Sensor Networks.	MSN	2007	DBLP DOI BibTeX RDF	Threshold zone, temporal-spatial correlation, wireless sensor networks, fault tolerance, event detection
1	Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu Cheng	CacheCompress: a novel approach for test data compression with cache for IP embedded cores.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton	Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.	ASP-DAC	2006	DBLP DOI BibTeX RDF	biclique covering, false subgraphs, multi-cycle subgraphs, static timing analysis, time shifting
1	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao	The Y architecture for on-chip interconnect: analysis and methodology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris	Unified quadratic programming approach for mixed mode placement.	ISPD	2005	DBLP DOI BibTeX RDF	mixed mode placement, discrete cosine transformation, quadratic programming
1	Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng	Integrated algorithmic logical and physical design of integer multiplier.	ASP-DAC	2005	DBLP DOI BibTeX RDF	booth, interconnect, partial product, TDM
1	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris	Improving the efficiency of static timing analysis with false paths.	ICCAD	2005	DBLP BibTeX RDF
1	Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng	A multiple level network approach for clock skew minimization with process variations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham	Floorplan representations: Complexity and connections.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Baxter permutation, Floorplan representation, O-tree, mosaic floorplan, number of combinations, twin binary trees
1	Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham	A hierarchical three-way interconnect architecture for hexagonal processors.	SLIP	2003	DBLP DOI BibTeX RDF	Y architecture, Y tree, interconnect architecture
1	Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng	Power network analysis using an adaptive algebraic multigrid approach.	DAC	2003	DBLP DOI BibTeX RDF	adaptive analysis, algebraic multigrid method, circuit simulation, power distribution network
1	Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu	An algebraic multigrid solver for analytical placement with layout based clustering.	DAC	2003	DBLP DOI BibTeX RDF	algebraic multigrid method, layout based clustering, analytical placement
1	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao	The Y-Architecture for On-Chip Interconnect: Analysis and Methodology.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham	Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.	ICCD	2002	DBLP DOI BibTeX RDF
1	Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng	Physical Planning Of On-Chip Interconnect Architectures.	ICCD	2002	DBLP DOI BibTeX RDF
1	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham	Revisiting floorplan representations.	ISPD	2001	DBLP DOI BibTeX RDF

Publications of "Bo Yao" ( http://dblp.L3S.de/Authors/Bo_Yao )