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Publications of "Bogdan F. Romanescu" ( http://dblp.L3S.de/Authors/Bogdan_F._Romanescu )

  Author page on DBLP  Author page in RDF  Community of Bogdan F. Romanescu in ASPL-2

Publication years (Num. hits)
2007 (2) 2008 (2) 2010 (2) 2011 (1)
Publication types (Num. hits)
article(2) inproceedings(5)
Venues (Conferences, Journals, ...)
PACT(2) ASPLOS(1) Conf. Computing Frontiers(1) HPCA(1) IEEE Micro(1) SIGARCH Computer Architecture ...(1)
Authors
Bogdan F. Romanescu(7) Daniel J. Sorin(7) Alvin R. Lebeck(3) Michael E. Bauer(3) Sule Ozev(3) Anne Bracy(1)
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Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin Address Translation Aware Memory Consistency. Search on Bibsonomy IEEE Micro The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin Specifying and dynamically verifying address translation-aware memory consistency. Search on Bibsonomy ASPLOS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF virtual memory, memory consistency, address translation, dynamic verification
1Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all. Search on Bibsonomy HPCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Bogdan F. Romanescu, Daniel J. Sorin Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. Search on Bibsonomy PACT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF lifetime performance, fault tolerance, reliability, multicore
1Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF microarchitecture, process variability
1Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin VariaSim: simulating circuits and systems in the presence of process variability. Search on Bibsonomy SIGARCH Computer Architecture News The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. Search on Bibsonomy PACT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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