Search results for "Booth's algorithm"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Chiou-Yng Lee, Yu-Hsin Chiu, Che Wun Chiou	New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
2	Jin-Hua Hong, Cheng-Wen Wu	Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Louis P. Rubinfield	A Proof of the Modified Booth's Algorithm for Multiplication.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Modified Booth's algorithm, multiplicand, multiplier, partial product
1	Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin	Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm.	Computers & Electrical Engineering	2005	DBLP DOI BibTeX RDF
1	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Sung-Ho Baik, Kyung-Nam Han, E. Yoon	A 230 MHz 8 tap programmable FIR filter using redundant binary number system.	ISCAS	1999	DBLP DOI BibTeX RDF
1	S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian	A GaAs IEEE Floating Point Standard Single Precision Multiplier.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating point multiplier, rounding algorithm, modified carry save array, GaAs technology
1	S. Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian	A 32-bit GaAs IEEE floating point multiplier using Trailing-1's rounding algorithm.	Electronic Technology Directions	1995	DBLP DOI BibTeX RDF
1	S. M. Aziz	A C-testable modified Booth's array multiplier.	VLSI Design	1995	DBLP DOI BibTeX RDF	C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
1	D. V. Poornaiah, P. V. Ananda Mohan	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
1	I-Chen Wu	A Fast 1-D Serial-Parallel Systolic Multiplier.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	Countercurrent data flow pattern, five-level multiplexer, five-level recorder, modified Booth's Algorithm, systolic multilier, VLSI, two's complement
1	Tom Rhyne, Noel R. Strader II	A Signed Bit-Sequential Multiplier.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	VLSI signal processing circuits, Bit-sequential multiplication, Booth's algorithm, carry-save arithmetic, computer arithmetic