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Publications of "Brian P. Degnan" ( http://dblp.L3S.de/Authors/Brian_P._Degnan )

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Publication years (Num. hits)
2005 (2) 2007 (1) 2009 (2) 2010 (5)
Publication types (Num. hits)
article(1) inproceedings(9)
Venues (Conferences, Journals, ...)
ISCAS(9) VLSI Design(1)
Authors
Brian P. Degnan(10) Paul E. Hasler(10) Craig Schlottmann(3) Richard B. Wunderlich(3) Arindam Basu(2) Aurele Balavoine(2) Bo Marr(2) Csaba Petre(2) David V. Anderson(2) Scott Koziol(2) Shubha Ramakrishnan(2) Stephen Brink(2) Brian J. Duffy(1) Christal Gordon(1) David N. Abramson(1) David W. Graham(1) More (+10 of total 18)
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Found 10 publication records. Showing 10 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Bo Marr, Jason George, Brian P. Degnan, David V. Anderson, Paul E. Hasler Error Immune Logic for Low-Power Probabilistic Computing. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Craig Schlottmann, Brian P. Degnan, David N. Abramson, Paul E. Hasler Reducing offset errors in MITE systems by precise floating gate programming. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Brian P. Degnan, Brian J. Duffy, Paul E. Hasler Crossbar switch matrix for floating-gate programming over large current ranges. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Scott Koziol, Craig Schlottmann, Arindam Basu, Stephen Brink, Csaba Petre, Brian P. Degnan, Shubha Ramakrishnan, Paul E. Hasler, Aurele Balavoine Hardware and software infrastructure for a family of floating-gate based FPAAs. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Scott Koziol, Craig Schlottmann, Arindam Basu, Stephen Brink, Csaba Petre, Brian P. Degnan, Shubha Ramakrishnan, Paul E. Hasler, Aurele Balavoine Live demonstration: Hardware and software infrastructure for a family of floating-gate based FPAAs. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson An Asynchronously Embedded Datapath for Performance Acceleration and Energy Efficiency. Search on Bibsonomy ISCAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Brian P. Degnan, Richard B. Wunderlich, Paul E. Hasler Passgate Resistance Estimation based on the Compact EKV Model and Effective Mobility. Search on Bibsonomy ISCAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Richard B. Wunderlich, Brian P. Degnan, Paul E. Hasler Capacitively-Biased Floating-Gate CMOS: a New Logic Family. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler Indirect programming of floating-gate transistors. Search on Bibsonomy ISCAS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
1Brian P. Degnan, Richard B. Wunderlich, Paul E. Hasler Programmable floating-gate techniques for CMOS inverters. Search on Bibsonomy ISCAS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
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