Search results for "Bus encoding"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	bit transitions, bus-encoding scheme, high impedance state, simultaneous switching noise (SSN), spatial and temporal redundancy, low power, delay, encoder, decoder, crosstalk noise, inductive coupling
3	Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu, Qinru Qiu	Low-power bus encoding using an adaptive hybrid algorithm.	DAC	2006	DBLP DOI BibTeX RDF	data probabilistic distribution, delayed bus, weighted code mapping, window based change detection, low power, adaptive algorithm, bus encoding
3	Alberto Bocca, Sabino Salerno, Enrico Macii, Massimo Poncino	Energy-efficient bus encoding for LCD displays.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	LCD displays, digital display interfaces, low-power bus encoding
3	P. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam	A Bus Encoding Technique for Power and Cross-talk Minimization.	VLSI Design	2004	DBLP DOI BibTeX RDF	Cross-talk, Limited Weight Codes, Transition Signalling, Encoding techniques, memoryless bus encoding, pipelining, Low Power Design
2	Madhu Mutyam	Selective shielding technique to eliminate crosstalk transitions.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	power consumption, Crosstalk, switching activity, bus encoding
2	Truong Quang Vinh, Young-Chul Kim	A low power crosstalk-free bus encoding using genetic algorithm.	AICCSA	2008	DBLP DOI BibTeX RDF
2	K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas	Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas	Bus encoding schemes for minimizing delay in VLSI interconnects.	SBCCI	2007	DBLP DOI BibTeX RDF	bus encoding technique, crosstalk class, delay, encoder, decoder, VLSI interconnects
2	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).	ISCAS	2007	DBLP DOI BibTeX RDF
2	Madhu Mutyam	Selective shielding: a crosstalk-free bus encoding technique.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Charbel J. Akl, Magdy A. Bayoumi	Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects.	ASP-DAC	2007	DBLP DOI BibTeX RDF	transition skew coding, global on-chip interconnects, bus encoding technique, encoding latencies, decoding latencies, 90 nm
2	Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner	Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Satoshi Komatsu, Masahiro Fujita	An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Avnish R. Brahmbhatt, Jingyi Zhang, Qinru Qiu, Qing Wu	Adaptive low-power bus encoding based on weighted code mapping.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Hsun-Chieh Yu, Rung-Bin Lin	Is more redundancy better for on-chip bus encoding.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester	Bus encoding for total power reduction using a leakage-aware buffer configuration.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.	ISQED	2005	DBLP DOI BibTeX RDF
2	Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan	A Novel Bus Encoding Scheme from Energy and Crosstalk Efficiency Perspective for AMBA Based Generic SoC Systems.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	A tunable bus encoder for off-chip data buses.	ISLPED	2005	DBLP DOI BibTeX RDF	TUBE, data bus, data bus encoding, tunable bus encoder
2	Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino	Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces.	ISLPED	2004	DBLP DOI BibTeX RDF	LCD displays, digital display interfaces, low-power bus encoding
2	Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw	Leakage-and crosstalk-aware bus encoding for total power reduction.	DAC	2004	DBLP DOI BibTeX RDF	low power, encoding, leakage reduction
2	Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim	Resource-constrained low-power bus encoding with crosstalk delay elimination.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Siu-Kei Wong, Chi-Ying Tsui	Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus.	DATE	2004	DBLP DOI BibTeX RDF
2	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan	Power efficient encoding techniques for off-chip data buses.	CASES	2003	DBLP DOI BibTeX RDF	FV, FV-MSB-LSB, data bus, low power, bus encoding
2	Heiko Zimmer, Axel Jantsch	A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	fault tolerance, network-on-chip, bus encoding
2	Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino	Energy-efficient data scrambling on memory-processor interfaces.	ISLPED	2003	DBLP DOI BibTeX RDF	data scrambling, bus encoding, power attacks
2	Claudia Kretzschmar, Robert Siegmund, Dietmar Müller	Low Power Encoding Techniques for Dynamically Reconfigurable Hardware.	The Journal of Supercomputing	2003	DBLP DOI BibTeX RDF	transition minimizing bus encoding, low power, dynamic reconfiguration
2	Claudia Kretzschmar, Robert Siegmund, Dietmar Müller	A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram	Software-Only Bus Encoding Techniques for an Embedded System.	VLSI Design	2002	DBLP DOI BibTeX RDF	memory bus encoding, bus activity minimization, CompactFlash, low power, Flash memory, LCD
2	Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram	ALBORZ: Address Level Bus Power Optimization. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	Low power bus encoding, limited-weight codes, codebook-based codes
2	Haris Lekatsas, Jörg Henkel	ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs.	VLSI Design	2002	DBLP DOI BibTeX RDF	bus invert, low power, bus encoding
2	Wei-Chung Cheng, Massoud Pedram	Memory Bus Encoding for Low Power: A Tutorial.	ISQED	2001	DBLP DOI BibTeX RDF
2	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer	Power optimization of core-based systems by address bus encoding.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Chih-Peng Fan, Chia-Hao Fang	Efficient RC low-power bus encoding methods for crosstalk reduction.	Integration	2011	DBLP DOI BibTeX RDF
1	Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown	Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan	Interframe Bus Encoding Technique and Architecture for MPEG-4 AVC/H.264 Video Compression.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Shanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu	A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bus-invert, coupling, interconnect delay
1	Nallamothu Satyanarayana, A. Vinaya Babu, Madhu Mutyam	Delay-efficient bus encoding techniques.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	Tunable and Energy Efficient Bus Encoding Techniques.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign Bit Reduction Encoding For Low Power Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Signed multiplier, Sign extension, FIR filter, Power reduction, Energy reduction, Bus encoding
1	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	Energy-efficient encoding techniques for off-chip data buses.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power data buses, bus switching, internal capacitances, encoding
1	Jingyi Zhang, Qing Wu, Qinru Qiu	Bus encoding for simultaneous delay and energy optimization.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Srinivasa Vemuru, Ahmed Elkammar, Norman Scheinberg	Subbus Control Line Impact on Effectiveness of Bus Encoding Schemes.	CDES	2008	DBLP BibTeX RDF
1	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
1	Krishnan Sundaresan, Nihar R. Mahapatra	Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.	ISQED	2008	DBLP DOI BibTeX RDF	Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
1	T. Venkata Kalyan, Madhu Mutyam, P. Vijaya Sankara Rao	Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu	Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.	VTS	2008	DBLP DOI BibTeX RDF	Codeword Selection, Crosstalk Avoidance, Reliable Bus
1	Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang	A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan	Interframe Bus Encoding Technique for Low Power Video Compression.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	H. W. Lin, K. C. Wei	Low Power Bus Encoding Technique Considering Coupling Effects.	IMECS	2007	DBLP BibTeX RDF
1	Chandan Giri, Santanu Chattopadhyay	Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Shanq-Jang Ruan, Shang-Fang Tsai, Yu-Ting Pai	Design and Analysis of Low Power Dynamic Bus Based on RLC simulation.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Sharath Jayaprakash, Nihar R. Mahapatra	Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Ahmed Elkammar, Norman Scheinberg, Srinivasa Vemuru	Bus Encoding Scheme To Eliminate Unwanted Signal Transitions.	DELTA	2006	DBLP DOI BibTeX RDF
1	Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King	Hierarchical value cache encoding for off-chip data bus.	ISLPED	2006	DBLP DOI BibTeX RDF	data bus encoding, hierarchical value cache, energy
1	Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin	On-chip bus thermal analysis and optimization.	DATE	2006	DBLP DOI BibTeX RDF
1	Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra	Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	address bus, low power, encoding, energy dissipation
1	Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling	Optimal memoryless encoding for low power off-chip data buses.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Qingli Zhang, Jinxiang Wang, Yizheng Ye	Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Shang-Fang Tsai, Shanq-Jang Ruan	DS2IS: Dictionary-based Segmented Signal Inversion Scheme for Low Power Dynamic Bus Design.	ICIT	2006	DBLP DOI BibTeX RDF
1	Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn	Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Ashutosh Chakraborty, Enrico Macii, Massimo Poncino	Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu	Low-Power Data Address Bus Encoding Method.	CDES	2005	DBLP BibTeX RDF
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign bit reduction encoding for low power applications.	DAC	2005	DBLP DOI BibTeX RDF	signed multiplier, sing extension, low power, switching activity, bus encoding
1	Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner	A linear model for high-level delay estimation in VDSM on-chip interconnects.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Peter Petrov, Alex Orailoglu	Low-power instruction bus encoding for embedded processors.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Ahmed Elkammar, Srinivasa Vemuru, Norman Scheinberg	A Bus Encoding Scheme to Reduce Power Consuming Signal Transitions.	ESA/VLSI	2004	DBLP BibTeX RDF
1	Jayapreetha Natesan, Damu Radhakrishnan	A Novel Bus Encoding Technique for Low Power VLSI.	ESA/VLSI	2004	DBLP BibTeX RDF
1	Claudia Kretzschmar, Markus Scheithauer, Dietmar Müller	Adaptive Bus Encoding Schemes for Power-Efficient Data Transfer in DSM Environments.	DIPES	2004	DBLP BibTeX RDF
1	Tien-Fu Chen, Tsung-Ming Hsieh, Chun-Li Wei	Unified bus encoding by stream reconstruction with variable strides.	ISCAS	2004	DBLP BibTeX RDF
1	Siu-Kei Wong, Chi-Ying Tsui	Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus.	ISCAS	2004	DBLP BibTeX RDF
1	Kanishka Lahiri, Anand Raghunathan	Power analysis of system-level on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, network-on-chip, low-power design, power analysis, communication architectures
1	Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger	Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.	DATE	2004	DBLP DOI BibTeX RDF
1	Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag	Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses.	ICCD	2004	DBLP DOI BibTeX RDF
1	Madhu Mutyam	Preventing Crosstalk Delay using Fibonacci Representation.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Byung-Soo Choi, Jeong-A. Lee, Dong-Soo Har	High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan	A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi	A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi	A Genetic Approach To Bus Encoding.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Enrico Macii, Massimo Poncino, Sabino Salerno	Combining wire swapping and spacing for low-power deep-submicron buses.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	low-power design, physical design, crosstalk, bus encoding
1	Ketan N. Patel, Igor L. Markov	Error-correction and crosstalk avoidance in DSM busses.	SLIP	2003	DBLP DOI BibTeX RDF	DSM busses, error-correction, crosstalk noise, bus encoding
1	Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf	Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses.	DATE	2003	DBLP DOI BibTeX RDF
1	Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu	On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf	A dictionary-based en/decoding scheme for low-power data buses.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick	Encoded-Low Swing Technique for Ultra Low Power Interconnect.	FPL	2003	DBLP DOI BibTeX RDF
1	Wei-Chung Cheng, Massoud Pedram	Power-Aware Bus Encoding Techniques for I/O and Data Buses in an Embedded System.	Journal of Circuits, Systems, and Computers	2002	DBLP DOI BibTeX RDF
1	K. Basu, Alok N. Choudhary, Jayaprakash Pisharath, Mahmut T. Kandemir	Power protocol: reducing power dissipation on off-chip data buses.	MICRO	2002	DBLP DOI BibTeX RDF
1	Tiehan Lv, Wayne Wolf, Jörg Henkel, Haris Lekatsas	An Adaptive Dictionary Encoding Scheme for SOC Data Buses.	DATE	2002	DBLP DOI BibTeX RDF
1	Unni Narayanan, Ki-Seok Chung, Taewhan Kim	Enhanced bus invert encodings for low-power.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Haris Lekatsas, Wayne Wolf, Yuan Xie	Code Compression for VLIW Processors Using Variable-to-Fixed Coding.	ISSS	2002	DBLP DOI BibTeX RDF	assembly-level analysis, performance estimation, superscalar architectures
1	Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang	Narrow bus encoding for low-power DSP systems.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram	Irredundant address bus encoding for low power.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Bret M. Victor, Kurt Keutzer	Bus Encoding to Prevent Crosstalk Delay.	ICCAD	2001	DBLP BibTeX RDF
1	Massoud Pedram	Power optimization and management in embedded systems.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Benjamin Bishop, V. Lyuboslavsky, Narayanan Vijaykrishnan, Mary Jane Irwin	Design considerations for databus charge recovery.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Claudia Kretzschmar, Robert Siegmund, Dietmar Müller	Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses.	PATMOS	2000	DBLP DOI BibTeX RDF
1	Naehyuck Chang, Kwanho Kim, Jinsung Cho	Bus encoding for low-power high-performance memory systems.	DAC	2000	DBLP DOI BibTeX RDF
1	Youngsoo Shin, Kiyoung Choi	Narrow bus encoding for low power systems.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	William Fornaciari, M. Polentarutti, Donatella Sciuto, Cristina Silvano	Power optimization of system-level address buses based on software profiling.	CODES	2000	DBLP DOI BibTeX RDF