| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | D. Li, X. L. Sun, C. L. Liu |
An exact solution method for unconstrained quadratic 0-1 programming: a geometric approach.  |
J. Global Optimization  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | X. L. Sun, C. L. Liu, D. Li, J. J. Gao |
On duality gap in binary quadratic programming. |
J. Global Optimization |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | C. L. Liu |
I attended the nineteenth design automation conference. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | C. L. Liu |
The High Walls have Crumpled. (PDF / PS) |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Pinar, C. L. Liu |
Compacting sequences with invariant transition frequencies. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
Sequence compaction, graph algorithms, power estimation |
| 1 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang |
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang |
Noise-aware interconnect power optimization in domino logic synthesis. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu |
Logic transformation for low-power synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
logic transformation, power estimation model, low power, Logic synthesis |
| 1 | Ki-Seok Chung, Taewhan Kim, C. L. Liu |
A Complete Model for Glitch Analysis in Logic Circuits. |
Journal of Circuits, Systems, and Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang |
Domino logic synthesis based on implication graph. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu |
Synthesis and Optimization of Combinational Interface Circuits. |
VLSI Signal Processing |
2002 |
DBLP DOI BibTeX RDF |
embedded systems, logic circuit, interface synthesis |
| 1 | Prashant Saxena, C. L. Liu |
Optimization of the maximum delay of global interconnects duringlayer assignment. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
Architecture driven circuit partitioning. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Seok Chung, Taewhan Kim, C. L. Liu |
G-vector: A New Model for Glitch Analysis in Logic Circuits. |
VLSI Signal Processing |
2001 |
DBLP DOI BibTeX RDF |
synthesis, power estimation, logic circuits, glitches |
| 1 | Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang |
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu |
Binary decision diagram with minimum expected path length. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Prashant Saxena, C. L. Liu |
A postprocessing algorithm for crosstalk-driven wire perturbation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang |
Noise-aware power optimization for on-chip interconnect. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhyung Um, Taewhan Kim, C. L. Liu |
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang |
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Peichen Pan, C. L. Liu |
Partial Scan with Preselected Scan Signals. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
design for testability, retiming, partial scan, Digital testing |
| 1 | Prashant Saxena, C. L. Liu |
Crosstalk Minimization Using Wire Perturbations. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Prashant Saxena, Peichen Pan, C. L. Liu |
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | C. L. Liu |
From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. (PDF / PS) |
IEEE Real-Time Systems Symposium |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu |
Logic Transformation for Low Power Synthesis. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chaeryung Park, Taewhan Park, C. L. Liu |
An efficient data path synthesis algorithm for behavioral-level power optimization. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Junhyung Um, Taewhan Kim, C. L. Liu |
Optimal allocation of carry-save-adders in arithmetic optimization. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Ki-Wook Kim, C. L. Liu, Sung-Mo Kang |
Implication graph based domino logic synthesis. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Peichen Pan, C. L. Liu |
Optimal clock period FPGA technology mapping for sequential circuits. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis |
| 1 | Peichen Pan, Arvind K. Karandikar, C. L. Liu |
Optimal clock period clustering for sequential circuits with retiming. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Chaeryung Park, Taewhan Kim, C. L. Liu |
Register Allocation - A Hierarchical Reduction Approach. |
VLSI Signal Processing |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Seok Chung, C. L. Liu |
Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Unni Narayanan, Peichen Pan, C. L. Liu |
Low power logic synthesis under a general delay model. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Prashant Saxena, C. L. Liu |
A performance-driven layer assignment algorithm for multiple interconnect trees. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
Architecture driven circuit partitioning. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Pinar, C. L. Liu |
Power invariant vector sequence compaction. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Peichen Pan, Sai-keung Dong, C. L. Liu |
Optimal Graph Constraint Reduction for Symbolic Layout Compaction. |
Algorithmica |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu |
Routing for symmetric FPGAs and FPICs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Anmol Mathur, C. L. Liu |
Timing-driven placement for regular architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Chau-Shen Chen, TingTing Hwang, C. L. Liu |
Low Power FPGA Design - A Re-engineering Approach. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Unni Narayanan, C. L. Liu |
Low power logic synthesis for XOR based circuits. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
vlsi cad logic synthesis, XOR logic, Fixed Polarity Reed Muller Forms, Huffman Algorithm, low power design |
| 1 | Arvind K. Karandikar, Peichen Pan, C. L. Liu |
Optimal Clock Period Clustering for Sequential Circuits with Retiming. |
ICCD |
1997 |
DBLP BibTeX RDF |
|
| 1 | Peichen Pan, Weiping Shi, C. L. Liu |
Area Minimization for Hierarchical Floorplans. |
Algorithmica |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu |
Low power realization of finite state machines - a decomposition approach. |
ACM Trans. Design Autom. Electr. Syst. |
1996 |
DBLP DOI BibTeX RDF |
decomposition of finite state machines, lower power design, state assignment |
| 1 | Tong Gao, C. L. Liu |
Minimum crosstalk channel routing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Taewhan Kim, C. L. Liu |
An integrated algorithm for incremental data path synthesis. |
VLSI Signal Processing |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu |
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. |
Euro-Par, Vol. I |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Peichen Pan, C. L. Liu |
Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. |
DAC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiangfeng Chen, Peichen Pan, C. L. Liu |
Desensitization for Power Reduction in Sequential Circuits. |
DAC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Peichen Pan, C. L. Liu |
Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. |
FPGA |
1996 |
DBLP DOI BibTeX RDF |
FPGAs, sequential circuits, retiming, technology mapping, look-up table, logic replication, clock period |
| 1 | Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu |
An algorithm for synthesis of system-level interface circuits. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
System-Level Design Issues, Optimization, Algorithm, Interface Synthesis |
| 1 | Ran Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu |
Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. |
IEEE Trans. Parallel Distrib. Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Peichen Pan, C. L. Liu |
Area minimization for floorplans. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Peichen Pan, C. L. Liu |
Partial Scan with Pre-selected Scan Signals. |
DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Anmol Mathur, K. C. Chen, C. L. Liu |
Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. |
FPGA |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Anmol Mathur, K. C. Chen, C. L. Liu |
Re-engineering of timing constrained placements for regular architectures. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging |
| 1 | Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu |
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Srilata Raman, C. L. Liu, Larry G. Jones |
A delay driven FPGA placement algorithm. |
EURO-DAC |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Yachyang Sun, C. L. Liu |
Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. |
DAC |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong Gao, C. L. Liu |
Minimum crosstalk switchbox routing. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Anmol Mathur, C. L. Liu |
Compression-relaxation: a new approach to performance driven placement for regular architectures. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Peichen Pan, Weiping Shi, C. L. Liu |
Area minimization for hierarchical floorplans. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Kuan Shih, Jane W.-S. Liu, C. L. Liu |
Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. |
IEEE Trans. Software Eng. |
1993 |
DBLP DOI BibTeX RDF |
modified rate-monotonic algorithm, periodic jobs, deferred deadlines, semi-static priority-driven algorithm, time instant, old requests, current request, independent jobs, request deadline, deterministic scheduling theory, scheduling, real-time systems, real-time systems, computational complexity, embedded systems, operating system, scheduling algorithms, job scheduling, operating systems (computers), multiprogramming, feasibly scheduled |
| 1 | Jason Cong, Bryan Preas, C. L. Liu |
Physical models and efficient algorithms for over-the-cell routing in standard cell design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Peichen Pan, Sai-keung Dong, C. L. Liu |
Optimal Graph Constraint Reduction for Symbolic Layout Compaction. |
DAC |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Taewhan Kim, C. L. Liu |
Utilization of Multiport Memories in Data Path Synthesis. |
DAC |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu |
Routing for symmetric FPGAs and FPICs. |
ICCAD |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong Gao, C. L. Liu |
Minimum crosstalk channel routing. |
ICCAD |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong Gao, Pravin M. Vaidya, C. L. Liu |
A Performance Driven Macro-Cell Placement Algorithm. |
DAC |
1992 |
DBLP BibTeX RDF |
|
| 1 | Peichen Pan, C. L. Liu |
Area minimization for general floorplans. |
ICCAD |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Yachyang Sun, C. L. Liu |
An Area Minimizer for Floorplans with L-Shaped Regions. |
ICCD |
1992 |
DBLP BibTeX RDF |
|
| 1 | Jason Cong, C. L. Liu |
On the k-layer planar subset and topological via minimization problems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Philip K. McKinley, Nany Hasan, Ran Libeskind-Hadas, C. L. Liu |
Disjoint Covers in Replicated Heterogeneous Arrays. |
SIAM J. Discrete Math. |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu |
A Channel Router for Single Layer Customization Technology. |
ICCAD |
1991 |
DBLP BibTeX RDF |
|
| 1 | Tong Gao, Pravo M. Vaidya, C. L. Liu |
A New Performance Driven Placement Algorithm. |
ICCAD |
1991 |
DBLP BibTeX RDF |
|
| 1 | Taewhan Kim, Jane W.-S. Liu, C. L. Liu |
A Scheduling Algorithm for Conditional Resource Sharing. |
ICCAD |
1991 |
DBLP BibTeX RDF |
|
| 1 | Jason Cong, C. L. Liu |
Over-the-cell channel routing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Xianjin Yao, C. L. Liu |
Solution of a module orientation and rotation problem. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, C. L. Liu |
On the k-layer planar subset and via minimization problems. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Bryan Preas, C. L. Liu |
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Nany Hasan, C. L. Liu |
Fault covers in reconfigurable PLAs. |
FTCS |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | D. F. Wong, C. L. Liu |
Floorplan Design of VLSI Circuits. |
Algorithmica |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Xianjin Yao, Masaaki Yamada, C. L. Liu |
A new approach to the pin assignment problem. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaojun Shen, Y. Z. Cai, C. L. Liu, Clyde P. Kruskal |
Generalized latin squares I. |
Discrete Applied Mathematics |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Ran Libeskind-Hadas, C. L. Liu |
Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Martin D. F. Wong, C. L. Liu |
A new approach to three- or four-layer channel routing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1988 |
DBLP DOI BibTeX RDF |
|
| 1 | Xianji Yao, Masaaki Yamada, C. L. Liu |
A New Approach to the Pin Assignment Problem. |
DAC |
1988 |
DBLP BibTeX RDF |
|
| 1 | Nany Hasan, C. L. Liu |
Minimum fault coverage in reconfigurable arrays. |
FTCS |
1988 |
DBLP DOI BibTeX RDF |
|
| 1 | D. F. Wong, C. L. Liu |
Array Optimization for VLSI Synthesis. |
DAC |
1987 |
DBLP DOI BibTeX RDF |
|
| 1 | J. L. Lewandowski, C. L. Liu, Jane W.-S. Liu |
An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem. |
J. Algorithms |
1986 |
DBLP DOI BibTeX RDF |
|
| 1 | D. F. Wong, C. L. Liu |
A new algorithm for floorplan design. |
DAC |
1986 |
DBLP DOI BibTeX RDF |
|
| 1 | Prakash V. Ramanan, C. L. Liu |
Permutation Representation of k-Ary Trees. |
Theor. Comput. Sci. |
1985 |
DBLP DOI BibTeX RDF |
|
| 1 | J. R. Egan, C. L. Liu |
Bipartite Folding and Partitioning of a PLA. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1984 |
DBLP DOI BibTeX RDF |
|
| 1 | Prakash V. Ramanan, Jitender S. Deogun, C. L. Liu |
A Personnel Assignment Problem. |
J. Algorithms |
1984 |
DBLP DOI BibTeX RDF |
|
| 1 | W.-D. Wei, C. L. Liu |
On a Periodic Maintenance Problem. |
Oper. Res. Lett. |
1983 |
DBLP BibTeX RDF |
|
| 1 | D. T. Lee, C. L. Liu, C. K. Wong |
(g 0, g 1, ... g k)-Trees and Unary OL Systems. |
Theor. Comput. Sci. |
1983 |
DBLP DOI BibTeX RDF |
|
| 1 | C. L. Liu, Jane W.-S. Liu, Arthur L. Liestman |
Scheduling with Slack Time. |
Acta Inf. |
1982 |
DBLP DOI BibTeX RDF |
|
| 1 | J. R. Egan, C. L. Liu |
Optimal bipartite folding of PLA. |
DAC |
1982 |
DBLP DOI BibTeX RDF |
|
| 1 | C. L. Liu |
Generation of trees. |
CLAAP |
1980 |
DBLP BibTeX RDF |
|
| 1 | Jane W.-S. Liu, C. L. Liu |
Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors. |
Acta Inf. |
1978 |
DBLP DOI BibTeX RDF |
|
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