| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar |
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip.  |
ACM Trans. Embedded Comput. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen |
Test Strategies for Low-Power Devices. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti |
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle (eds.) |
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008 |
ISLPED |
2008 |
DBLP BibTeX RDF |
|
| 1 | Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan |
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan |
Memory Architecture Exploration Framework for Cache Based Embedded SOC. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen |
Test Strategies for Low Power Devices. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy |
Low-Power Hierarchical Scan Test for Multiple Clock Domains. |
J. Low Power Electronics |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar |
A critical-path-aware partial gating approach for test power reduction. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
partial gating, scan cell gating, Low-power testing, scan testing |
| 1 | Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler |
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
Variation-Tolerant, Power-Safe Pattern Generation. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
low-power ATPG, process variation, IR drop, peak power, power profiling |
| 1 | C. P. Ravikumar, Jari Nurmi |
Conference Reports. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
Melvin Breuer, SOC 2006, SoC design, ITC |
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti |
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan |
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
Low Power ATPG, Glitch Power, IR Drop, Peak Power, Power-profiling |
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan |
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar |
Conference Reports. |
IEEE Design & Test of Computers |
2006 |
DBLP DOI BibTeX RDF |
Logic Soft Errors, conference report |
| 1 | Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar |
Enhanced launch-off-capture transition fault testing. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy |
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar |
Partial Gating Optimization for Power Reduction During Test Application. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic |
At-Speed Transition Fault Testing With Low Speed Scan Enable. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar |
A Framework for Distributed and Hierarchical Design-for-Test. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar |
A self-checking signature scheme for checking backdoor security attacks in Internet. |
J. High Speed Networks |
2004 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar, Graham Hetherington |
A Holistic Parallel and Hierarchical Approach towards Design-For-Test. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
Experiments and Case Studies, Practical Test Engineering |
| 1 | C. P. Ravikumar |
Multiprocessor Architectures for Embedded System-on-chip Applications. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Aman Kokrady, C. P. Ravikumar |
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop |
| 1 | C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra |
Mutual Testing based on Wavelet Transforms. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
Mutual Testing, Discrete Wavelet Transform, At-Speed Testing |
| 1 | Aman Kokrady, C. P. Ravikumar |
Static Verification of Test Vectors for IR Drop Failure. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri |
An Evolutionary Scheme for Cosynthesis of Real-Time Systems. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
stochastic task scheduling, hierarchical genetic algorithm, multiprocessor architectures, embedded real-time systems, Hardware software co-synthesis |
| 1 | Rahul Kumar, C. P. Ravikumar |
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Power Estimation, Leakage Power, Linear Regression, Deep Submicron |
| 1 | Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri |
Improvement of ASIC Design Processes. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Rahul Kumar |
Divide-and-Conquer IDDQ Testing for Core-Based System Chips. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Mirza Mohd. Sufyan Beg, C. P. Ravikumar |
Measuring the Quality of Web Search Results. |
JCIS |
2002 |
DBLP BibTeX RDF |
|
| 1 | V. Sankara Subramanian, C. P. Ravikumar |
Estimating Crosstalk From Vlsi Layouts. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Vineet Sahula, C. P. Ravikumar |
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishal Dalal, C. P. Ravikumar |
Software Power Optimizations In An Embedded System. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
A scheme for multiple on-chip signature checking for embedded SRAMS. |
Journal of Systems Architecture |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Kannah, C. P. Ravikumar |
Functional Testing of Microprocessors with Graded Fault Coverage. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Anil Sharma, C. P. Ravikumar |
Efficient Implementation of ADPCM Codec. |
VLSI Design |
2000 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma |
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Chakraverty, C. P. Ravikumar |
A Stochastic Framework for Co-synthesis of Real-Time Systems. |
LCTES |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar |
High-Performance Cluster Computing. Volume 1: Architecutes and Systems. Volume 2: Programming and Applications. |
Scalable Computing: Practice and Experience |
1999 |
DBLP BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Built-in Self Test Based on Multiple On-Chip Signature Checking. |
J. Electronic Testing |
1999 |
DBLP DOI BibTeX RDF |
multiple signature comparison testing, BIST, aliasing probability |
| 1 | Nishit Narang, Girish Kumar, C. P. Ravikumar |
Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications. |
HiPC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Meeta Sharma, Prachi Jain |
Design of WDM Networks for Delay-Bound Multicasting. |
HiPC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra |
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Rohit Sharma, C. P. Ravikumar |
Design Issues in Synthesis of Reusable Cores. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
Deign Reuse, CORDIC Arithmetic and Core Testability, Embedded Cores |
| 1 | C. P. Ravikumar, Ajay Mittal |
Hierarchical Delay Fault Simulation. |
VLSI Design |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Manish Sharma, R. K. Patney |
Improving the Diagnosability of Digital Circuits. |
VLSI Design |
1999 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar, Rajneesh Bajpai |
Source-based delay-bounded multicasting in multimedia networks. |
Computer Communications |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | R. Trobec, C. P. Ravikumar |
Parallel Methods for Vlsi Layout Design. |
IEEE Concurrency |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. |
J. Electronic Testing |
1998 |
DBLP DOI BibTeX RDF |
mutual checking, multiple signature testing, self loops, built-in self test, aliasing |
| 1 | Nidhi Agrawal, C. P. Ravikumar |
Adaptive Routing Based on Deadlock Recovery. |
Euro-Par |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, N. Satya Prasad |
Evaluating BIST Architectures for Low Power. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar |
An Evolutionary Approach to System Redesign. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
System Redesign, Intellectual Property Reuse, Genetic Algorithm, Component Reuse, System-level Synthesis |
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Hybrid Testing Schemes Based on Mutual and Signature Testing. |
VLSI Design |
1998 |
DBLP BibTeX RDF |
|
| 1 | Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar |
Freedom: Statistical Behavioral Estimation of System Energy and Power. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
On-Chip Signature Checking for Embedded Memories. |
VLSI Design |
1998 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar, Sumit Gupta, Akshay Jajoo |
Synthesis of Testable RTL Designs. |
VLSI Design |
1998 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar, Tarun Rai, Varun Verma |
Kautz graphs as attractive logical topologies in multihop lightwave networks. |
Computer Communications |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Nitin Agrawal, Parul Agarwal |
Hierarchical Delay Test Generation. |
J. Electronic Testing |
1997 |
DBLP DOI BibTeX RDF |
delay test generation, path selection, hierarchical testing |
| 1 | Nidhi Agrawal, C. P. Ravikumar |
An Euler Path Based Technique for Deadlock-free Multicasting. (PDF / PS) |
ICPP |
1997 |
DBLP DOI BibTeX RDF |
Euler-Path, Routing, Multicasting, Multicomputers, Virtual Channels, Deadlock-free |
| 1 | C. P. Ravikumar, R. Aggarwal, C. Sharma |
A Graph-Theoretic Approach for Register File Based Synthesis. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Vikas Jain, Anurag Dod |
Faster Fault Simulation Through Distributed Computing. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar |
Rapid Synthesis of Multi-Chip Systems. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
Efficient Implementation of Multiple On-Chip Signature Checking. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
A scheme for multiple on-chip signature checking for embedded SRAMs. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Nidhi Agrawal, C. P. Ravikumar |
Fault-tolerant routing in multiply twisted cube topology. |
Journal of Systems Architecture |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, R. Aggarwal |
Parallel search-and-learn techniques and graph coloring. |
Knowl.-Based Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar |
Efficient Delay Test Generation for Modular Circuits. |
Great Lakes Symposium on VLSI |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, V. Saxena |
Synthesis of Testable Pipelined Datapaths Using Genetic Search. |
VLSI Design |
1996 |
DBLP BibTeX RDF |
|
| 1 | Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar |
A Novel BIST Architecture With Built-in Self Check. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora |
Estimation of Power from Module-level Netlists. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Rajamani Rajarajan |
Genetic Algorithms for Scan Path Design. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Naresh Vedi |
Heuristic and neural algorithms for mapping tasks to a reconfigurable array. |
Microprocessing and Microprogramming |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal |
A STAFAN-like functional testability measure for register-level circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model |
| 1 | C. P. Ravikumar, Hemant Joshi |
HISCOAP: a hierarchical testability analysis tool. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model |
| 1 | C. P. Ravikumar |
Parallel search-and-learn technique for solving large scale travelling-salesperson problems. |
Knowl.-Based Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, H. Rasheed |
Simulated Annealing for Target-Oriented Scan. |
VLSI Design |
1994 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar |
Solving VLSI physical design problems on a vector machine. |
Computer-Aided Design |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, A. Kuchlous, G. Manimaran |
Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network. |
ICPP |
1993 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar |
A Parallel Search-and-Learn Technique for Solving Large Scale TSP. |
ICTAI |
1993 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar |
Interval partition with bounded overlap. |
Computer-Aided Design |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | C. P. Ravikumar, Lalit M. Patnaik |
Performance improvement of simulated annealing algorithms. |
Comput. Syst. Sci. Eng. |
1990 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar, Sarma Sastry |
Parallel Placement on Hypercube Architecture. |
ICPP |
1989 |
DBLP BibTeX RDF |
|
| 1 | C. P. Ravikumar, Lalit M. Patnaik |
An Architecture for CSP and Its Simulation. |
ICPP |
1987 |
DBLP BibTeX RDF |
|
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