Search results for "C.-J. Richard Shi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	C.-J. Richard Shi	Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Bo Hu, C.-J. Richard Shi	Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Lingzhi Liu, C.-J. Richard Shi	Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Lihong Zhang, C.-J. Richard Shi, Yingtao Jiang	Symmetry-aware placement with transitive closure graphs for analog layout design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Cherry Wakayama, Wolf Kohn, Zelda B. Zabinsky, C.-J. Richard Shi	A quantum-dot light-harvesting architecture using deterministic phase control.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Yu-Te Liao, C.-J. Richard Shi	A 6-11GHz multi-phase VCO design with active inductors.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Lili Zhou, Cherry Wakayama, C.-J. Richard Shi	CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Pavel V. Nikitin, C.-J. Richard Shi	VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial.	Integration	2007	DBLP DOI BibTeX RDF
1	Guoyong Shi, Weiwei Chen, C.-J. Richard Shi	A Graph Reduction Approach to Symbolic Circuit Analysis.	ASP-DAC	2007	DBLP DOI BibTeX RDF	symbolic analog circuit simulator, symbolic circuit analysis, recursive sign determination algorithm, binary decision diagram, graph reduction
1	Ming Su, Lili Zhou, C.-J. Richard Shi	Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.	ICCD	2007	DBLP DOI BibTeX RDF
1	Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi	Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.	ICCD	2007	DBLP DOI BibTeX RDF
1	C.-J. Richard Shi, Michael W. Tian, Guoyong Shi	Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Zhao Li, C.-J. Richard Shi	SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Multilevel symmetry-constraint generation for retargeting large analog layouts.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Zhao Li, C.-J. Richard Shi	A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Guoyong Shi, Bo Hu, C.-J. Richard Shi	On symbolic model order reduction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Lei Yang, C.-J. Richard Shi	FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits.	Integration	2006	DBLP DOI BibTeX RDF
1	Zhao Li, C.-J. Richard Shi	A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi	A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Bo Hu, C.-J. Richard Shi	Improved automatic differentiation method for efficient model compiler.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi	Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.	ICCAD	2006	DBLP DOI BibTeX RDF	analog/RF integrated circuits, layout automation, layout symmetry, design reuse, parasitics
1	Vikram Jandhyala, Yasuo Kuga, David J. Allstot, C.-J. Richard Shi	Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design.	MSE	2005	DBLP DOI BibTeX RDF
1	Lei Yang, Cherry Wakayama, C.-J. Richard Shi	Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	jitter noise, PLL, phase noise, frequency synthesizer
1	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Template-driven parasitic-aware optimization of analog integrated circuit layouts.	DAC	2005	DBLP DOI BibTeX RDF	analog layout automation, optimization, sensitivity, parasitics
1	Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi	An FPGA implementation of low-density parity-check code decoder with multi-rate capability.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Automatic Device Layout Generation for Analog Layout Retargeting.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Zhao Li, C.-J. Richard Shi	An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation.	DATE	2005	DBLP DOI BibTeX RDF
1	Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe	Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Bo Hu, C.-J. Richard Shi	Fast-yet-accurate PVT simulation by combined direct and iterative methods.	ICCAD	2005	DBLP BibTeX RDF
1	Sheldon X.-D. Tan, C.-J. Richard Shi	Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Pavel V. Nikitin, Vikram Jandhyala, Daniel White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway	Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow.	ISQED	2004	DBLP DOI BibTeX RDF
1	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi	Correct-by-construction layout-centric retargeting of large analog designs.	DAC	2004	DBLP DOI BibTeX RDF	analog integrated circuit design, analog layout automation, analog synthesis and optimization, layout symmetry
1	Guoyong Shi, C.-J. Richard Shi	Parametric reduced order modeling for interconnect analysis.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi	Hierarchical extraction and verification of symmetry constraints for analog layout automation.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi	CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi	Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Bo Wan, C.-J. Richard Shi	Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation.	DATE	2004	DBLP DOI BibTeX RDF	Model Compiler, Hierarchical Multi-dimensional Table Lookup, Optimization, Circuit Simulation, Abstract-Syntax-Tree
1	Zhao Li, C.-J. Richard Shi	A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks.	ISCAS	2004	DBLP BibTeX RDF
1	Sheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee	Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Sheldon X.-D. Tan, C.-J. Richard Shi	Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi	IPRAIL - intellectual property reuse-based analog IC layout automation.	Integration	2003	DBLP DOI BibTeX RDF
1	Sheldon X.-D. Tan, C.-J. Richard Shi	Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis.	Integration	2003	DBLP DOI BibTeX RDF
1	Pavel V. Nikitin, Winnie Yam, C.-J. Richard Shi	Parametric Equivalent Circuit Extraction for VLSI Structures.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Alicia Manthe, Zhao Li, C.-J. Richard Shi	Symbolic analysis of analog circuits with hard nonlinearity.	DAC	2003	DBLP DOI BibTeX RDF	PWL, circuit nonlinearity, symbolic analysis
1	Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram	Symbolic Analysis of Nonlinear Analog Circuits.	DATE	2003	DBLP DOI BibTeX RDF
1	Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi	Automatic analog layout retargeting for new processes and device sizes.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Sambuddha Bhattacharya, C.-J. Richard Shi	Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Zhao Li, C.-J. Richard Shi	SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects.	ICCAD	2003	DBLP DOI BibTeX RDF	SPICE
1	Lei Yang, C.-J. Richard Shi	FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Vikram Jandhyala, Yong Wang, Dipanjan Gope, C.-J. Richard Shi	Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
1	C.-J. Richard Shi, Sheldon X.-D. Tan	Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Sheldon X.-D. Tan, C.-J. Richard Shi	Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling.	DAC	2001	DBLP DOI BibTeX RDF
1	Dragos Lungeanu, C.-J. Richard Shi	Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits.	ICCD	2001	DBLP BibTeX RDF
1	Alicia Manthe, C.-J. Richard Shi	Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis.	ICCD	2001	DBLP BibTeX RDF
1	C.-J. Richard Shi, Sheldon X.-D. Tan	Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Sheldon X.-D. Tan, C.-J. Richard Shi	Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Tao Pi, C.-J. Richard Shi	Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits.	DAC	2000	DBLP DOI BibTeX RDF
1	Xiang-Dong Tan, C.-J. Richard Shi	Symbolic circuit-noise analysis and modeling with determinant decision diagrams.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Tao Pi, C.-J. Richard Shi	Analog-testability analysis by determinant-decision-diagrams based symbolic analysis.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Dragos Lungeanu, C.-J. Richard Shi	Parallel and Distributed VHDL Simulation.	DATE	2000	DBLP DOI BibTeX RDF
1	Youcef Bourai, C.-J. Richard Shi	Layout Compaction for Yield Optimization via Critical Area Minimization.	DATE	2000	DBLP DOI BibTeX RDF
1	C.-J. Richard Shi, Michael W. Tian	Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	interval mathematics, uncertainty, process variations, sensitivity, worst-case analysis
1	C.-J. Richard Shi, Janusz A. Brzozowski	A Characterization of Signed Hypergraphs and Its Applications to VLSI Via Minimization and Logic Synthesis.	Discrete Applied Mathematics	1999	DBLP DOI BibTeX RDF
1	Xiang-Dong Tan, C.-J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan	Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings.	DAC	1999	DBLP DOI BibTeX RDF
1	Xiang-Dong Tan, C.-J. Richard Shi	Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis.	ASP-DAC	1999	DBLP DOI BibTeX RDF
1	Youcef Bourai, C.-J. Richard Shi	Symmetry Detection for Automatic Analog-Layout Recycling.	ASP-DAC	1999	DBLP DOI BibTeX RDF
1	Xiang-Dong Tan, C.-J. Richard Shi	Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams.	DATE	1999	DBLP DOI BibTeX RDF
1	Dragos Lungeanu, C.-J. Richard Shi	Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization.	ICCAD	1999	DBLP BibTeX RDF
1	C.-J. Richard Shi, Janusz A. Brzozowski	Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	cluster-cover, logic minimizaiton, self-checking logic design, topological routing, NP-completeness, state assignment
1	C.-J. Richard Shi	Entity Overloading for Mixed-Signal Abstraction in VHDL.	J. Inf. Sci. Eng.	1998	DBLP BibTeX RDF
1	Nihal J. Godambe, C.-J. Richard Shi	Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	behavioral fault modeling, noise, fault modeling, fault simulation, jitter, analog test
1	C.-J. Richard Shi, Michael W. Tian	Automatic Test Generation for Linear Analog Circuits under Parameter Variations.	ASP-DAC	1998	DBLP BibTeX RDF
1	C.-J. Richard Shi	Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial).	ASP-DAC	1998	DBLP BibTeX RDF
1	Michael W. Tian, C.-J. Richard Shi	Nonlinear Analog DC Fault Simulation by One-Step Relaxation. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Michael W. Tian, C.-J. Richard Shi	Efficient DC Fault Simulation of Nonlinear Analog Circuits.	DATE	1998	DBLP DOI BibTeX RDF
1	C.-J. Richard Shi, Anthony Vannelli, Jiri Vlach	Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning.	J. Heuristics	1997	DBLP DOI BibTeX RDF
1	Michael W. Tian, C.-J. Richard Shi	Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances.	DAC	1997	DBLP DOI BibTeX RDF
1	Nihal J. Godambe, C.-J. Richard Shi	Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS.	VTS	1997	DBLP DOI BibTeX RDF	behavioral level noise modeling, jitter simulation, mixed-signal hardware description language, phase-locked loops, voltage-controlled oscillator, power supply noise, phase noise, VHDL-AMS, catastrophic faults, top down design, integrated circuit noise
1	C.-J. Richard Shi, Xiang-Dong Tan	Symbolic analysis of large analog circuits with determinant decision diagrams.	ICCAD	1997	DBLP DOI BibTeX RDF
1	Olivier Coudert, C.-J. Richard Shi	Exact Dichotomy-based Constrained Encodi. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	Sequential logic synthesis, constrained state encoding, clique partition, set covering, dichotomy, ZBDD
1	C.-J. Richard Shi, Janusz A. Brzozowski	A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	Jiri Vlach, James A. Barby, Anthony Vannelli, T. Talkhan, C.-J. Richard Shi	Group delay as an estimate of delay in logic.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF

Publications of "C.-J. Richard Shi" ( http://dblp.L3S.de/Authors/C.-J._Richard_Shi )