Search results for "CGRA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Yoonjin Kim, Rabi N. Mahapatra	Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems.	DAC	2009	DBLP DOI BibTeX RDF	coarse-grained reconfigurable architecture (CGRA), computing hierarchy, embedded systems
2	Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula	Enabling Multithreading on CGRAs.	ICPP	2011	DBLP DOI BibTeX RDF	CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique
2	Yongjun Park, Hyunchul Park, Scott A. Mahlke	CGRA express: accelerating execution using dynamic operation fusion.	CASES	2009	DBLP DOI BibTeX RDF	latency-constrained, subgraph accelerator, modulo scheduling, coarse-grained reconfigurable architecture
1	Pranav Vaidya, Jaehwan John Lee	A Novel Multicontext Coarse-Grained Reconfigurable Architecture (CGRA) For Accelerating Column-Oriented Databases.	TRETS	2011	DBLP DOI BibTeX RDF
1	Ming Yan, Ziyu Yang, Liu Yang, Lei Liu, Sikun Li	Practical and Effective Domain-Specific Function Unit Design for CGRA.	ICCSA	2011	DBLP DOI BibTeX RDF
1	Kyuseung Han, Jong Kyung Paek, Kiyoung Choi	Acceleration of control flow on CGRA using advanced predicated execution.	FPT	2010	DBLP DOI BibTeX RDF
1	Muhammad Ali Shami, Ahmed Hemani	Control Scheme for a CGRA.	SBAC-PAD	2010	DBLP DOI BibTeX RDF
1	Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck	SPR: an architecture-adaptive CGRA mapping tool.	FPGA	2009	DBLP DOI BibTeX RDF	modulo graph, spr, static sharing, clustering, scheduling, routing, placement, pathfinder
1	Yoonjin Kim, Rabi N. Mahapatra	Dynamic context management for low power coarse-grained reconfigurable architecture.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	context word, embedded systems, system-on-chip (soc), digital signal processing, coarse-grained reconfigurable architecture, configuration cache
1	Taewook Oh, Bernhard Egger, Hyunchul Park, Scott A. Mahlke	Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures.	LCTES	2009	DBLP DOI BibTeX RDF	software pipelining, placement and routing, coarse-grained reconfigurable architectures
1	Yan Guo, Sanyou Y. Zeng, Lishan Kang, Gang Liu, Nannan Hu, Kuo Zhao	A Route System Based on Genetic Algorithm for Coarse-Grain Reconfigurable Architecture.	ISICA	2009	DBLP DOI BibTeX RDF	resources-constrained multi-pair shortest path problem in directed graphs, Multi-pair path encoding, Genetic algorithm, Coarse-grain reconfigurable architecture
1	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.	The Journal of Supercomputing	2009	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, High productivity tools, Modulo scheduling, Architectural exploration, Compiler techniques
1	Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi	Compiling custom instructions onto expression-grained reconfigurable architectures.	CASES	2008	DBLP DOI BibTeX RDF	horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures
1	Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek	SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.	DATE	2008	DBLP DOI BibTeX RDF
1	Yoonjin Kim, Rabi N. Mahapatra	A New Array Fabric for Coarse-Grained Reconfigurable Architecture.	DSD	2008	DBLP DOI BibTeX RDF
1	Carlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker	Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures.	FCCM	2008	DBLP DOI BibTeX RDF
1	Yoonjin Kim, Rabi N. Mahapatra	Reusable context pipelining for low power coarse-grained reconfigurable architecture.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Thomas Lenart, Henrik Svensson, Viktor Öwall	Modeling and exploration of a reconfigurable architecture for digital holographic imaging.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest	Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.	VLSI Design	2008	DBLP DOI BibTeX RDF	Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design
1	Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest	Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Matthias Hartmann, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic, Christian Hochberger, Bjorn De Sutter	Still Image Processing on Coarse-Grained Reconfigurable Array Architectures.	ESTImedia	2007	DBLP DOI BibTeX RDF
1	Yoonjin Kim, Rabi N. Mahapatra	Dynamically compressible context architecture for low power coarse-grained reconfigurable array.	ICCD	2007	DBLP DOI BibTeX RDF
1	Akira Hatanaka, Nader Bagherzadeh	A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek	Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture.	ISLPED	2006	DBLP DOI BibTeX RDF	coarse-grained reconfigurable architecture (CGRA), context pipelining, temporal mapping, low power, system-on-chip (SoC), loop pipelining, configuration cache, spatial mapping
1	Leipo Yan, Thambipillai Srikanthan, Niu Gang	Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures.	LCTES	2006	DBLP DOI BibTeX RDF	CGRA, VLIW, hardware/software partitioning, delay estimation, area estimation
1	Hyunchul Park, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke	Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures.	CASES	2006	DBLP DOI BibTeX RDF	graph embedding, modulo scheduling, coarse-grained reconfigurable architecture
1	Sunil Shukla, Neil W. Bergmann, Jürgen Becker	QUKU: A Two-Level Reconfigurable Architecture.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Sunil Shukla, Neil W. Bergmann, Jürgen Becker	QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection.	ARC	2006	DBLP DOI BibTeX RDF
1	Song Li-Guo, Jiang Yu-Xian	A Route System Based on Ant Colony for Coarse-Grain Reconfigurable Architecture.	ICNC	2006	DBLP DOI BibTeX RDF