Search results for "CICC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Wei-Kai Chan, Yu-Hsiang Tseng, Pei-Kuei Tsung, Tzu-Der Chuang, Yi-Min Tsai, Wei-Yin Chen, Liang-Gee Chen, Shao-Yi Chien	ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor.	CICC	2011	DBLP DOI BibTeX RDF
1	Michael Georgas, Jonathan Leu, Benjamin Moss, Chen Sun, Vladimir Stojanovic	Addressing link-level design tradeoffs for integrated photonic interconnects.	CICC	2011	DBLP DOI BibTeX RDF
1	Jing Guo, Jiageng Huang, George Jie Yuan, Jessica Ka-Yan Law, Chi-Kong Yeung, Mansun Chan	A 38.6nV/Hz0.5 -59.6dB THD dual-band micro-electrode array signal acquisition IC.	CICC	2011	DBLP DOI BibTeX RDF
1	Tom Malzbender	Understanding the Antikythera Mechanism.	CICC	2011	DBLP DOI BibTeX RDF
1	Zhenfei Peng, Shanshan Yang, Yong Feng, Zhiliang Hong, Bill Liu	An 80% peak efficiency, 410mW, single supply rail powered Class-I linear audio amplifier.	CICC	2011	DBLP DOI BibTeX RDF
1	Jong-In Kim, Wan Kim, Barosaim Sung, Seung-Tak Ryu	A time-domain latch interpolation technique for low power flash ADCs.	CICC	2011	DBLP DOI BibTeX RDF
1	Ozgur Inac, Andy Fung, Gabriel M. Rebeiz	Double-balanced 130-180 GHz passive and balanced 145-165 GHz active mixers in 45 nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Youngmin Park, David D. Wentzloff	An all-digital PLL synthesized from a digital standard cell library in 65nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen	Power-efficient I/O design considerations for high-bandwidth applications.	CICC	2011	DBLP DOI BibTeX RDF
1	Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya	Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs.	CICC	2011	DBLP DOI BibTeX RDF
1	Mohammad Hekmat, David K. Su, Bruce A. Wooley	A quadrature LO generator using bidirectionally-coupled oscillators for 60-GHz applications.	CICC	2011	DBLP DOI BibTeX RDF
1	Lingkai Kong, Yue Lu, Elad Alon	A multi-GHz area-efficient comparator with dynamic offset cancellation.	CICC	2011	DBLP DOI BibTeX RDF
1	Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano	0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.	CICC	2011	DBLP DOI BibTeX RDF
1	Le Zheng, Kuanfu Chen, Wentai Liu	A non-coherent versatile DPSK receiver for high channel-density neural prosthesis.	CICC	2011	DBLP DOI BibTeX RDF
1	Ming-Feng Huang	A discrete-time charge-domain filter with bandwidth calibration for LTE application.	CICC	2011	DBLP DOI BibTeX RDF
1	Yu Bi, Simon de Graaf, Nick van der Meijs	Enhanced sensitivity computation for BEM based capacitance extraction using the Schur complement technique.	CICC	2011	DBLP DOI BibTeX RDF
1	John R. Long, Y. Zhao, Y. Jin, W. Wu, Marco Spirito	Circuit technologies for mm-wave wireless systems on silicon.	CICC	2011	DBLP DOI BibTeX RDF
1	Edward K. F. Lee	A capacitor-based AC-DC step-up converter for biomedical implants.	CICC	2011	DBLP DOI BibTeX RDF
1	Bei Peng, Guanzhong Huang, Hao Li, Peiyuan Wan, Pingfen Lin	A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Xiaochen Yang, Jin Liu	An open-loop 10GHz 8-phase clock generator in 65nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Nicholas Olson, Nathan Jack, Vrashank Shukla, Elyse Rosenbaum	CDM-ESD induced damage in components using stacked-die packaging.	CICC	2011	DBLP DOI BibTeX RDF
1	Kun-Hin To, Vishal P. Trivedi	A 76-81GHz transmitter with 10dBm output power at 125 °C for automotive radar in 65nm bulk CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Siavash Fallahi, Delong Cui, Deyi Pi, Rose Zhu, Greg Unruh, Marcel Lugthart, Afshin Momtaz	A 19 mW/lane Serdes transceiver for SFI-5.1 application.	CICC	2011	DBLP DOI BibTeX RDF
1	Michael Clinton, Clive Bittlestone, G. Girishankar, Viet Le, Vinod Menezes	Design and technology interaction beyond 32nm.	CICC	2011	DBLP DOI BibTeX RDF
1	Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif	Electrically-driven retargeting for nanoscale layouts.	CICC	2011	DBLP DOI BibTeX RDF
1	Subramanian S. Iyer, T. Kirihata, John E. Barth Jr.	Three Dimensional integration - Considerations for memory applications.	CICC	2011	DBLP DOI BibTeX RDF
1	Ja-Yol Lee, Mi-Jeong Park, Byonghoon Mhin, Seong-Do Kim, Moon-Yang Park, Hyunku Yu	A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation.	CICC	2011	DBLP DOI BibTeX RDF
1	Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj	A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	E. Ryman, A. Emrich, S. Andersson, J. Riesbeck, Lars J. Svensson, Per Larsson-Edefors	3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry.	CICC	2011	DBLP DOI BibTeX RDF
1	Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi	Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs.	CICC	2011	DBLP DOI BibTeX RDF
1	Sanjeev K. Maheshwari, Emerson Fang, Sanjeev Aggarwal	32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL.	CICC	2011	DBLP DOI BibTeX RDF
1	Yu-Huei Lee, Ming-Yan Fan, Wei-Chung Chen, Ke-Horng Chen, Sheng-Fa Liu, Pao-Hsien Chiu, Sandy Chen, Chun-Yu Shen, Ming-Ta Hsieh, Huai-An Li	A near-zero cross-regulation single-inductor bipolar-output (SIBO) converter with an active-energy-correlation control for driving cholesteric-LCD.	CICC	2011	DBLP DOI BibTeX RDF
1	Pyoungwon Park, Dongmin Park, SeongHwan Cho	A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL.	CICC	2011	DBLP DOI BibTeX RDF
1	Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto	A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition.	CICC	2011	DBLP DOI BibTeX RDF
1	Feng Zhao, Fa Foster Dai	A 0.6V quadrature VCO with optimized capacitive coupling for phase noise reduction.	CICC	2011	DBLP DOI BibTeX RDF
1	Harmeet Bhugra	Frequency reference challenges - a systemic view.	CICC	2011	DBLP DOI BibTeX RDF
1	Trent McConaghy	High-dimensional statistical modeling and analysis of custom integrated circuits (invited paper).	CICC	2011	DBLP DOI BibTeX RDF
1	Paul Merolla, John Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra S. Modha	A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm.	CICC	2011	DBLP DOI BibTeX RDF
1	Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto	Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy.	CICC	2011	DBLP DOI BibTeX RDF
1	Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez	A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer.	CICC	2011	DBLP DOI BibTeX RDF
1	Omeed Momeni, Ehsan Afshari	A high gain 107 GHz amplifier in 130 nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Ralph Mason, Justin Fortier, Chris DeVries	Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking.	CICC	2011	DBLP DOI BibTeX RDF
1	S. H. Yang, J. Y. Sheu, M. K. Ieong, M. H. Chiang, T. Yamamoto, J. J. Liaw, S. S. Chang, Y. M. Lin, T. L. Hsu, J. R. Hwang, J. K. Ting, C. H. Wu, K. C. Ting, F. C. Yang, C. M. Liu, I. L. Wu, Y. M. Chen, S. J. Chent, K. S. Chen, J. Y. Cheng, M. H. Tsai, W. Chang, R. Chen, C. C. Chen, T. L. Lee, C. K. Lin, S. C. Yang, Y. M. Sheu, J. T. Tzeng, L. C. Lu, S. M. Jang, C. H. Diaz, Yuh-Jier Mii	28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications.	CICC	2011	DBLP DOI BibTeX RDF
1	Vivek De	Energy efficient designs with wide dynamic range.	CICC	2011	DBLP DOI BibTeX RDF
1	Muhammad Adnan, Ehsan Afshari	A low conversion loss passive frequency doubler.	CICC	2011	DBLP DOI BibTeX RDF
1	Ranjit Gharpurey	Managing linearity in radio front-ends.	CICC	2011	DBLP DOI BibTeX RDF
1	Justin Shi, Ying-Chih Hsu, Eric G. Soenen, Alan Roth, Justin Gaither	A wide-range DC/DC converter with 2nd order digital compensation and direct battery connection in 40nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Joseph N. Y. Aziz, Ark-Chew Wong, Andrew Chen, Derek Tam	A 65nm CMOS self-terminated open-drain IDAC line driver suitable for fast Ethernet applications.	CICC	2011	DBLP DOI BibTeX RDF
1	Shang-Fu Yeh, Jin-Yi Lin, Chih-Cheng Hsieh, Ka-Yi Yeh, Chung-Chi Jim Li	A new CMOS image sensor readout structure for 3D integrated imagers.	CICC	2011	DBLP DOI BibTeX RDF
1	Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera	A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay.	CICC	2011	DBLP DOI BibTeX RDF
1	Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman	A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.	CICC	2011	DBLP DOI BibTeX RDF
1	Jae Hyuk Jang, David F. Berdy, Jangjoon Lee, Dimitrios Peroulis, Byunghoo Jung	A wireless sensor node for condition monitoring powered by a vibration energy harvester.	CICC	2011	DBLP DOI BibTeX RDF
1	Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu	Digital clock and data recovery circuit design: Challenges and tradeoffs.	CICC	2011	DBLP DOI BibTeX RDF
1	Yousef Shakhsheer, Sudhanshu Khanna, Kyle Craig, Saad Arrabi, John Lach, Benton H. Calhoun	A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V.	CICC	2011	DBLP DOI BibTeX RDF
1	Yanjie Wang, Hua Wang, Christopher D. Hull, Shmuel Ravid	A transformer-based broadband I/O matching-balun-T/R switch front-end combo scheme in standard CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Jan Craninckx, Jonathan Borremans, Mark Ingels	SAW-less software-defined radio transceivers in 40nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Tsung-Che Lu, Lan-Da Van, Chi-Sheng Lin, Chun-Ming Huang	A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications.	CICC	2011	DBLP DOI BibTeX RDF
1	Shen Wang, Dong Sam Ha, Beomsup Kim, Vipul Chawla	A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generation.	CICC	2011	DBLP DOI BibTeX RDF
1	Yasumichi Takai, Masanori Hashimoto, Takao Onoye	Power gating implementation for noise mitigation with body-tied triple-well structure.	CICC	2011	DBLP DOI BibTeX RDF
1	J. F. Buller, J. Fletcher, S. Meyers, M. Robinson, F. Tamayo, A. Prakash, D. Cabler	Band-gap circuit design challenges in high-performance 32-nm technology.	CICC	2011	DBLP DOI BibTeX RDF
1	Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim	A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Chun-wei Hsu, Karthik Tripurari, Shih-An Yu, Peter R. Kinget	A 2.2GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppression.	CICC	2011	DBLP DOI BibTeX RDF
1	Maryam Tabesh, Amin Arbabian, Ali M. Niknejad	60GHz low-loss compact phase shifters using a transformer-based hybrid in 65nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Philip K. T. Mok	High-efficient DC-DC converter design.	CICC	2011	DBLP DOI BibTeX RDF
1	Emmanuel Hardy, Hassan Ihs, Christian Dufaza, Stéphane Meillére, Rachid Bouchakour	A partial tree vector quantizer dynamic element matching technique for audio Δ-Σ converters.	CICC	2011	DBLP DOI BibTeX RDF
1	Sanghyeon Lee, Jeongseok Chae, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes	A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application.	CICC	2011	DBLP DOI BibTeX RDF
1	Jacob Postman, Patrick Chiang	Energy-efficient transceiver circuits for short-range on-chip interconnects.	CICC	2011	DBLP DOI BibTeX RDF
1	Rakesh Patel, Tom Andre, Aurangzeb Khan (eds.)	2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011	CICC	2011	DBLP BibTeX RDF
1	Jacob Rosenstein, Sebastian Sorgenfrei, Kenneth L. Shepard	Noise and bandwidth performance of single-molecule biosensors.	CICC	2011	DBLP DOI BibTeX RDF
1	Tsung-Yen Tsai, Gordon W. Roberts	Programmable phase/frequency generator for system debug and diagnosis using the IEEE 1149.1 test bus.	CICC	2011	DBLP DOI BibTeX RDF
1	Dragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, Geert Van der Plas	DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.	CICC	2011	DBLP DOI BibTeX RDF
1	Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L. Jones, Naresh R. Shanbhag	Low power and error resilient PN code acquisition filter via statistical error compensation.	CICC	2011	DBLP DOI BibTeX RDF
1	A. Elsayed, A. Elshennawy, A. Elmallah, A. Shaban, B. George, M. Elmala, A. Ismail, A. Wassal, M. Sakr, A. Mokhtar, M. Hafez, A. Hamed, M. Saeed, M. Samir, M. Hammad, M. Elkhouly, A. Kamal, M. Rabieah, A. Elghufaili, S. Shaibani, I. Hakami, T. Alanazi	A self-clocked ASIC interface for MEMS gyroscope with 1m°/s/√Hz noise floor.	CICC	2011	DBLP DOI BibTeX RDF
1	Xiwen Zhang, Hoi Lee	A reconfigurable 2× / 2.5× / 3× / 4× SC DC-DC regulator for enhancing area and power efficiencies in transcutaneous power transmission.	CICC	2011	DBLP DOI BibTeX RDF
1	Xiaohan Gong, Jinhua Ni, Zhiliang Hong, Bill Liu	An 80% peak efficiency, 0.84mW sleep power consumption, fully-integrated DC-DC converter with buck/LDO mode control.	CICC	2011	DBLP DOI BibTeX RDF
1	Caspar P. L. van Vroonhoven, Kofi A. A. Makinwa	Thermal diffusivity sensing: A new temperature sensing paradigm.	CICC	2011	DBLP DOI BibTeX RDF
1	Sheng-Li Huang, Yo-Sheng Lin, Jen-How Lee	A Low-Power and low-noise 21∼29 GHz ultra-wideband receiver front-end in 0.18 µm CMOS technology.	CICC	2011	DBLP DOI BibTeX RDF
1	Ahmed Ashry, Hassan Aboushady	A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΔΣ ADC with a FoM of 1pJ/bit in 130nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Jianlei Shi, Brian P. Otis	A sub-100µW 2GHz differential colpitts CMOS/FBAR VCO.	CICC	2011	DBLP DOI BibTeX RDF
1	Peiyuan Wang, Xiang Chen, Yiran Chen, Hai Helen Li, Seung H. Kang, Xiaochun Zhu, Wenqing Wu	A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.	CICC	2011	DBLP DOI BibTeX RDF
1	H. Hedayati, Mohamed Mobarak, G. Varin, P. Meunier, P. Gamand, Edgar Sánchez-Sinencio, Kamran Entesari	A fully integrated highly linear efficient power amplifier in 0.25µm BiCMOS technology for wireless applications.	CICC	2011	DBLP DOI BibTeX RDF
1	Ali Hajimiri	Timing inaccuracy of clocks.	CICC	2011	DBLP DOI BibTeX RDF
1	Philip M. Chopp, Anas A. Hamoui	A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz.	CICC	2011	DBLP DOI BibTeX RDF
1	Bangda Yang, Brian Drost, Sachin Rao, Pavan Kumar Hanumolu	A high-PSR LDO using a feedforward supply-noise cancellation technique.	CICC	2011	DBLP DOI BibTeX RDF
1	L. Liu, D. Li, Y. Ye, L. Chen, Z. Wang	A 95dB SNDR audio ΔΣ modulator in 65nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Aritra Dey, David R. Allee	Amorphous silicon current steering digital to analog converter.	CICC	2011	DBLP DOI BibTeX RDF
1	Ru Huang, Runsheng Wang, Jing Zhuge, Changze Liu, Tao Yu, Liangliang Zhang, Xin Huang, Yujie Ai, Jinbin Zou, Yuchao Liu, Jiewen Fan, Huailin Liao, Yangyuan Wang	Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling.	CICC	2011	DBLP DOI BibTeX RDF
1	Jen-Chieh Tsai, Chi-Lin Chen, Yi-Ting Chen, Chia-Lung Ni, Chun-Yen Chen, Ke-Horng Chen, Chih-Jen Chen, Heng-Lin Pan	Perturbation on-time (POT) control and inhibit time control (ITC) in suppression of THD of power factor correction (PFC) design.	CICC	2011	DBLP DOI BibTeX RDF
1	Ch. Muller, Damien Deleruyelle, Olivier Ginez, Jean Michel Portal, Marc Bocquet	Design challenges for prototypical and emerging memory concepts relying on resistance switching.	CICC	2011	DBLP DOI BibTeX RDF
1	Michitaka Yoshino, Mitsuhiro Iwaide, Daigo Kuniyoshi, Hajime Ohtani, Akira Yasuda, Jun-ichi Okamura	A novel audio playback chip using digitally driven speaker architecture with 80%@-10dBFS power efficiency, 5.5W@3.3V supply and 100dB SNR.	CICC	2011	DBLP DOI BibTeX RDF
1	Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara	Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs.	CICC	2011	DBLP DOI BibTeX RDF
1	Shinichi Kubota, Nobuo Sasaki, Mohiuddin Hafiz, A. Toya, Takamaro Kikkawa	5 Gbps BPSK CMOS transmitter with on-chip antenna using Gaussian monocycle pulses.	CICC	2011	DBLP DOI BibTeX RDF
1	Ruslana Shulyzki, Karim Abdelhalim, A. Bagheri, C. M. Florez, Peter L. Carlen, Roman Genov	256-site active neural probe and 64-channel responsive cortical stimulator.	CICC	2011	DBLP DOI BibTeX RDF
1	Mehmet Parlak, James F. Buckwalter	A 2.9-dB noise figure, Q-band millimeter-wave CMOS SOI LNA.	CICC	2011	DBLP DOI BibTeX RDF
1	K. Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka	A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller.	CICC	2011	DBLP DOI BibTeX RDF
1	I.-Ning Ku, Zhiwei Xu, Yen-Cheng Kuan, Yen-Hsiang Wang, Mau-Chung Frank Chang	A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Nan Qi, Yang Xu, Baoyong Chi, Xiaobao Yu, Xing Zhang, Zhihua Wang	A dual-channel GPS/Compass/Galileo/GLONASS reconfigurable GNSS receiver in 65nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Mohamed H. Abu-Rahma, Ying Chen, Wing Sy, Wee Ling Ong, Leon Yeow Ting, Sei Seung Yoon, Michael Han, Esin Terzioglu	Characterization of SRAM sense amplifier input offset for yield prediction in 28nm CMOS.	CICC	2011	DBLP DOI BibTeX RDF
1	Navin K. Mishra, Manish Jain, Phuong Le, Sanku Mukherjee, Arul Sendhil, Amir Amirkhany	An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.	CICC	2011	DBLP DOI BibTeX RDF
1	N. Ruiz Amador, V. Huard, E. Pion, F. Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, L. Anghel	Bottom-up digital system-level reliability modeling.	CICC	2011	DBLP DOI BibTeX RDF

Publications at "CICC"( http://dblp.L3S.de/Venues/CICC )