Search results for "CMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	Keivan Navi, Daniel Etiemble	From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multivalued current mode CMOS circuits, voltage mode CMOS arithmetic operators, 3-valued current mode CMOS 2-input BSC adder, CMOS binary 4-2 counter, 1-digit Avizienis-like adder, adders, CMOS integrated circuits, integrated logic circuits, multivalued logic circuits, ternary logic, redundant number representation
6	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw	Library-less synthesis for static CMOS combinational logic circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance
6	Andreas G. Andreou, Kwabena Boahen	A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon retina, analog VLSI focal plane processor, phototransduction, local gain control, single chip system, vertebrate distal retina, ultra low power dissipation, n-well double metal double poly digital oriented CMOS technology, current-mode subthreshold CMOS, 48000 pixel, computer vision, VLSI, edge detection, CMOS integrated circuits, image sensors, contrast, edge enhancement, CMOS imager, focal planes, area efficiency, 1.2 micron
5	K. Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu	A Wideband CMOS LC-VCO Using Variable Inductor.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wideband CMOS LC-VCO, variable inductor, tunable CMOS voltage controlled oscillator, switched capacitors, 1.28 to 2.75 GHz, CMOS process, 0.18 micron
5	João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije	A 1.4 Gbit/s CMOS driver for 50 /spl Omega/ ECL systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	CMOS driver, ECL systems, speed performance, effective length, circuit operation, current source switching, output load, SDH/SONET system, CMOS-ECL convertor output buffer, 0.8 mum, 0.7 mum, 1.4 Gbit/s, 50 ohm, CMOS logic circuits, output buffer
5	Ayman I. Kayssi	Macromodeling C- and RC-loaded CMOS inverters for timing analysis.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling
5	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
5	Stephan P. Athan, David L. Landis, Sami A. Al-Arian	A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs.	VTS	1996	DBLP DOI BibTeX RDF	deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices
5	William C. Athas, Nestoras Tzartzanis	Energy recovery for low-power CMOS.	ARVLSI	1995	DBLP DOI BibTeX RDF	bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI
5	A. K. Jain, Mostafa H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
4	YuHua Cheng	A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	nano-CMOS IC design, IC design methodology, CMOS design technology platform, design-for-manufacturing (DFM), design-for-yield
4	Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi	Low-Power High-Speed 180-nm CMOS Clock Drivers.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.640 ns, CMOS clock drivers, register array, delay flip-flops, 251 muW, CMOS technology, power dissipation, delay time, 0.18 micron
4	Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier	Few electron devices: towards hybrid CMOS-SET integrated circuits.	DAC	2002	DBLP DOI BibTeX RDF	Iinverter, hybrid CMOS-SET Circuits, single-Electron transistors, ultimate CMOS, low power, quantizer, nanoelectronics
4	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
4	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
4	Mostafa H. Abd-El-Barr, Yanging Xu, Carl McCrosky	Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Transistor stuck-open fault, multi-level CMOS circuits testing, robust CMOS testing, test pattern generation, two-pattern test
4	Yinan N. Shen, Xiao-Tao Chen, Susumu Horiguchi, Fabrizio Lombardi	On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	CMOS fault model, multiple fault diagnosis, interconnection networks, fault diagnosis, lower bound, multistage interconnection networks, multistage interconnection networks, CMOS technology, stuck-open faults
4	Jonathan T.-Y. Chang, Edward J. McCluskey	SHOrt voltage elevation (SHOVE) test for weak CMOS ICs.	VTS	1997	DBLP DOI BibTeX RDF	short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC
4	Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen	Functional test pattern generation for CMOS operational amplifier.	VTS	1997	DBLP DOI BibTeX RDF	functional test pattern generation, CMOS operational amplifier, programmable gain/loss mixed signal circuit, op amp testing, IC testing, CMOS analogue integrated circuits
4	Alvernon Walker, Algernon P. Henry, Parag K. Lala	An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current
4	B. Chester Hwang	Trends of Key Advanced Device Technologies.	ARVLSI	1997	DBLP DOI BibTeX RDF	SIA roadmap, Sematech, TFSOI, graded-channel CMOS, complementary IC technology, 0.25 micron, CMOS integrated circuits, CMOS technology, Moore's law, GaAs, Si
4	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
4	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai	Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
4	Mostafa H. Abd-El-Barr, M. N. Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
4	Haluk Konuk, F. Joel Ferguson	An unexpected factor in testing for CMOS opens: the die surface.	VTS	1996	DBLP DOI BibTeX RDF	surface phenomena, electric charge, CMOS opens, die surface, RC interconnect, HSPICE simulations, trapped charge, floating gates, VLSI, integrated circuit testing, CMOS integrated circuits, integrated circuit modelling, circuit model
4	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
4	Masaru Sanada	A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq.	VTS	1996	DBLP DOI BibTeX RDF	CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration
4	Pradip Mandal, V. Visvanathan	Design of high performance two stage CMOS cascode op-amps with stable biasing.	VLSI Design	1996	DBLP DOI BibTeX RDF	two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability
4	A. B. Bhattacharyya, R. S. Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri	A micropower analog hearing aid on low voltage CMOS digital process.	VLSI Design	1996	DBLP DOI BibTeX RDF	differential amplifiers, automatic gain control, micropower analog hearing aid, low voltage CMOS digital process, adaptive biasing, MOS translinear loop circuit, degenerating linearising resistor, input differential stage, AGC block, conversion efficiency, 3 micron, 1.0 V, power consumption, CMOS analogue integrated circuits, hearing aids
4	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
4	Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III	A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.	ARVLSI	1995	DBLP DOI BibTeX RDF	high-speed fine-resolution pattern generation, data signals, edge placement, matched delays, MOSIS CMOS technology, 100 ps, 833 Mbit/s, architecture, delays, test pattern generators, network interfaces, CMOS digital integrated circuits, 1.2 micron
4	Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid, David A. Inglis, Eric R. Fossum	Standard CMOS active pixel image sensors for multimedia applications.	ARVLSI	1995	DBLP DOI BibTeX RDF	CMOS active pixel image sensors, single chip video cameras, color filter array, document capture, 1024 pixel, multimedia, multimedia systems, CMOS integrated circuits, image sensors, transistors, video cameras, gain
4	Hassan Ihs, Christian Dufaza	Tolerance DC bands of CMOS operational amplifier.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tolerance DC bands, CMOS operational amplifier, DC node voltages, data tolerance bands, foundry process fluctuations, DC branch current, OA, supply voltage, catastrophic defects, transistor connections, optimization, fault diagnosis, integrated circuit testing, fault detection, fault model, fault simulation, circuit optimisation, operational amplifiers, integrated circuit modelling, transistor size, CMOS analogue integrated circuits, design parameters
4	L. F. Fuller, C. Kraaijenvanger	Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education
4	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
4	John Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
4	Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira	Test preparation for high coverage of physical defects in CMOS digital ICs.	VTS	1995	DBLP DOI BibTeX RDF	high defect coverage, CMOS digital ICs, pseudo realistic faults generation, test quality assessment, tabloid, iceTgen, I/sub DDQ/ test generation, test preparation, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, CMOS digital integrated circuits, physical defects
4	J. A. Segura, Miquel Roca, Diego Mateo, Antonio Rubio	An approach to dynamic power consumption current testing of CMOS ICs.	VTS	1995	DBLP DOI BibTeX RDF	dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current
4	Josep Rius, Joan Figueras	Detecting I/sub DDQ/ defective CMOS circuits by depowering.	VTS	1995	DBLP DOI BibTeX RDF	I/sub DDQ/ defective CMOS circuits, depowering, fault detection capabilities, quiescent state, logic valves, discharge current, power supply line disconnection, logic testing, integrated circuit testing, fault location, CMOS logic circuits, capacitance
4	George A. Hadgis, P. R. Mukund	A novel CMOS monolithic analog multiplier with wide input dynamic range.	VLSI Design	1995	DBLP DOI BibTeX RDF	analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits
4	Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh	A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology.	VLSI Design	1995	DBLP DOI BibTeX RDF	integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation
4	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
4	Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito	A CMOS gate array with dynamic-termination GTL I/O circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	CMOS gate array, dynamic-termination GTL I/O circuits, triple-metal-layer process technology, push-pull output driver, dynamic termination receiver, 250 Mb/s data, stub line, terminated bus line, IDDQ testability, differential receiver, delay time overheads, 0.5 micron, 250 Mbit/s, logic testing, delays, CMOS logic circuits, logic arrays
4	Ram K. Krishnamurthy, Ramalingam Sridhar	A CMOS wave-pipelined image processor for real-time morphology . (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity
4	Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter	Combined DRAM and logic chip for massively parallel systems.	ARVLSI	1995	DBLP DOI BibTeX RDF	EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
4	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
4	S. G. Younis, Thomas F. Knight Jr.	Non-dissipative rail drivers for adiabatic circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics
4	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
4	K. Wayne Current	Memory Circuits for Multiple-Valued Logic Voltage Signals. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits
3	Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang 0003	Design considerations for variation tolerant multilevel CMOS/Nano memristor memory.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS/nano, memristor, multi level memories
3	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
3	Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky	Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	CMOS logic devices, reliability, Markov process, monte carlo method, poisson distribution, laplace transform
3	Ru Huang, HanMing Wu, Jinfeng Kang, DeYuan Xiao, XueLong Shi, Xia An, Yu Tian, Runsheng Wang, Liangliang Zhang, Xing Zhang, Yangyuan Wang	Challenges of 22 nm and beyond CMOS technology.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	22 nm technology node, device architectures, metal gate/high K dielectrics, ultra low K dielectrics, CMOS technology
3	Rajat Subhra Chakraborty, Swarup Bhunia	A study of asynchronous design methodology for robust CMOS-nano hybrid system design.	JETC	2009	DBLP DOI BibTeX RDF	CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
3	Liqiang Wang, Yan Shi, Zukang Lu, Huilong Duan	Miniaturized CMOS Imaging Module with Real-time DSP Technology for Endoscope and Laryngoscope Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	CMOS imaging module, Blackfin DSP, Minimally invasive instruments, Real-time video processing, Miniature
3	Kaushik Roy	Ultra low voltage CMOS.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive supply scaling, nano-scale cmos system, ultra low voltage design, ultra-dynamic voltage scaling
3	Hussain Alzaher, Noman Tasadduq	A CMOS low power current-mode polyphase filter.	ISLPED	2009	DBLP DOI BibTeX RDF	CMOS analog integrated circuits, low power current mode circuit, polyphase filter
3	Kevin Zhang	Circuit design in nano-scale CMOS era: opportunities & challenges.	ISLPED	2009	DBLP DOI BibTeX RDF	VLSI, CMOS, circuit
3	Kiyoo Itoh	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
3	Sergio Chaparro, Armando Ayala Pabón, Elkim Roa, Wilhelmus A. M. Van Noije	A merged RF CMOS LNA-Mixer design using geometric programming.	SBCCI	2009	DBLP DOI BibTeX RDF	LNA-Mixer, RF-CMOS inductors, optimization, analog circuits, geometric programming
3	Luiz Carlos Moreira, Wilhelmus A. M. Van Noije, Armando Ayala Pabón, Andrés Farfán-Peláez	Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology.	SBCCI	2009	DBLP DOI BibTeX RDF	cross inductors, rectangular inductors, RF CMOS
3	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design
3	Harika Manem, Garrett S. Rose	The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos-nano, fpga
3	Carl J. Anderson	One look into the future of CMOS chip design.	ISPD	2009	DBLP DOI BibTeX RDF	cmos design
3	Kelin J. Kuhn	CMOS scaling beyond 32nm: challenges and opportunities.	DAC	2009	DBLP DOI BibTeX RDF	high-k, CMOS, orientation, strain, metal-gate
3	Shekhar Borkar	Design perspectives on 22nm CMOS and beyond.	DAC	2009	DBLP DOI BibTeX RDF	nano, power, CMOS, variability
3	Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Ariana Filoramo, Christian Gamrat, Jean-Philippe Bourgoin	Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.	NanoNet	2009	DBLP DOI BibTeX RDF	Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
3	Mawahib Hussein Sulieman	On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations.	NanoNet	2009	DBLP DOI BibTeX RDF	Reliability, CMOS, threshold voltage, gates
3	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance
3	Lei Zhang, Zhiping Yu, Xiangqing He	A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors.	ISQED	2008	DBLP DOI BibTeX RDF	CMOS Process Fluctuations, Subthreshold Current Mirror, Discrete Martingale, Probability, Random Variable
3	Won-S. Oh, K. Park, J.-C. Choi, C. J. Kim, S. I. Lee, J. K. Moon	Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-µm CMOS Technology.	DELTA	2008	DBLP DOI BibTeX RDF	CMOS, OPTIC, RECEIVER, LA, TIA
3	Pablo Aguirre, Fernando Silveira	CMOS op-amp power optimization in all regions of inversion using geometric programming.	SBCCI	2008	DBLP DOI BibTeX RDF	optimization, CMOS, analog, geometric programming, automatic design
3	Victor Ariel Leal Sobral, Roberto Espinheira da Costa Bomfim, Robson Nunes de Lima, Ana Isabela Araújo Cunha	Systematic methodology for the design of Seevinck's CMOS log-domain integrators.	SBCCI	2008	DBLP DOI BibTeX RDF	CMOS integrators, companding circuits, log-domain integrators
3	Yarallah Koolivand, Seyed Morteza Alavi, Omid Shoaei	New technique in design of active rf cmos mixers for low flicker noise and high conversion gain.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	1.cmos mixer, direct conversion receiver, flicker noise, sub-threshold, ota, noise figure
3	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
3	Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas	Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, logic design, cmos gates
3	Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman	Full Open Defects in Nanometric CMOS.	VTS	2008	DBLP DOI BibTeX RDF	interconnect open, gate leakage current, CMOS
3	Bangli Liang, Tad A. Kwasniewski, Dianyong Chen	A 42-Gb/s Decision Circuit in 0.13µm CMOS.	CNSR	2008	DBLP DOI BibTeX RDF	CMOS CML, Shunt peaking, Split-resistor, Optical communication
3	Tadashi Ikeuchi, Tszshing Cheung, Hiroshi Onaka	The Latest Trend of Low Power High-Speed CMOS I/O Technology for Photonic Network.	SAINT	2008	DBLP DOI BibTeX RDF	High-speed input/output interfaces, low power, CMOS
3	Reza M. Rad, Mohammad Tehranipoor	Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.	JETC	2007	DBLP DOI BibTeX RDF	performance, FPGA, reliability, CMOS, Nanotechnology
3	Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan	Designing CMOS/molecular memories while considering device parameter variations.	JETC	2007	DBLP DOI BibTeX RDF	CMOS, nanotechnology, molecular electronics
3	M. Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Begueret	A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-in current sensor
3	Luca Benini, Carlotta Guiducci, Christian Paulus	Electronic Detection of DNA Hybridization: Toward CMOS Microarrays.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	CMOS microarrays, label-based DNA chip, label-free DNA chip, DNA hybridization
3	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
3	Yu Zhou, Shijo Thekkel, Swarup Bhunia	Low power FPGA design using hybrid CMOS-NEMS approach.	ISLPED	2007	DBLP DOI BibTeX RDF	hybrid CMOS-NEMS, low power, FPGA design
3	Walter J. Lancioni, Pablo A. Petrashin, Luis E. Toledo, Carlos Dualibe	A 9.6 kb/s CMOS FSK modem for data transmission through power lines.	SBCCI	2007	DBLP DOI BibTeX RDF	analog CMOS, power line transceiver, switched capacitor amplifier
3	Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider	A comparative study of CMOS gates with minimum transistor stacks.	SBCCI	2007	DBLP DOI BibTeX RDF	PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates
3	Ahmed A. Youssef	RF architectures in CMOS for the emerging wireless technologies: challenges and opportunities.	SBCCI	2007	DBLP DOI BibTeX RDF	integrated mobile communication systems, wireless, CMOS, RF
3	Leo Huf Campos Braga, Suzana Domingues, Milton F. Rocha, Leonardo Bruno de Sá, Fernando de Souza Campos, Filipe V. Santos, Antonio Carneiro Mesquita, Mário Vaz Silva, Jacobus W. Swart	Layout techniques for radiation hardening of standard CMOS active pixel sensors.	SBCCI	2007	DBLP DOI BibTeX RDF	radiation hardeness, CMOS, active pixel sensor
3	Fernando de Souza Campos, Ognian Marinov, Naser Faramarzpour, Fayçal Saffih, M. Jamal Deen, Jacobus W. Swart	A multisampling time-domain CMOS imager with synchronous readout circuit.	SBCCI	2007	DBLP DOI BibTeX RDF	fill-factor, dynamic range, CMOS imager, active pixel sensor
3	Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia	Viability of analog inner product operations in CMOS imagers.	SBCCI	2007	DBLP DOI BibTeX RDF	CMOS analog hardware, analog image processing, vector quantization
3	Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate
3	Linga Reddy Cenkeramaddi, Tajeshwar Singh, Trond Ytterdal	Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	CMUT-CMOS, analog front-end for CMUTs, charge sampling, sampling, CSA
3	Cosmin Popa	Linearized CMOS active resistor independent on the bulk effect.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	CMOS design, active resistor, linearity, area minimization
3	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Modeling and estimating leakage current in series-parallel CMOS networks.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage current modeling, static power dissipation, CMOS gates
3	M. Watanabe, F. Kobayashi	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
3	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
3	Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Masao Hotta	A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS.	ASP-DAC	2007	DBLP DOI BibTeX RDF	2.8 V, bandpass delta-sigma AD modulator, second-order AD modulator, multibit switched-capacitor AD modulator, low-IF receivers, wireless communication systems, signal-to-noise-and-distortion, complex bandpass filter, dynamic matching, data-weighted averaging algorithm, 78 kHz, 28.4 mW, CMOS process, 0.18 micron
3	S. Yoshitomi	Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	130 nm, RF-CMOS analog circuits, MOSFET models, EKV3.0 model, electro magnetic effects, building blocks, deep submicron
3	Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu	A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces.	ASP-DAC	2007	DBLP DOI BibTeX RDF	Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron