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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 7 occurrences of 6 keywords
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Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Benoit Gosselin, Mohamad Sawan |
An ultra low-power CMOS action potential detector.  |
ISCAS  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | C. M. Markan, Priti Gupta |
Neuromorphic building blocks for adaptable cortical feature maps.  |
VLSI-SoC  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Jihyun Lee, Yong-Bin Kim |
ASLIC: A low power CMOS analog circuit design automation.  |
Integration  |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Jihyun Lee, Yong-Bin Kim |
ASLIC: A Low Power CMOS Analog Circuit Design Automation.  |
ISQED  |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu |
A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach.  |
ISLPED  |
2004 |
DBLP DOI BibTeX RDF |
CMOS analog circuit, flash analog-to-digital converter, rail-to-rail, low power, comparator |
| 1 | Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi |
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique.  |
ISLPED  |
2003 |
DBLP DOI BibTeX RDF |
CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage |
| 1 | Razvan Ionita, Andrei Vladimirescu, Paul G. A. Jespers |
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.  |
PATMOS  |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Ravindranath Naiknaware, Terri S. Fiez |
CMOS analog circuit stack generation with matching constraints.  |
ICCAD  |
1998 |
DBLP DOI BibTeX RDF |
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| 1 | Ming-Jer Chen, Jib-Shin Ho |
A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
1997 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #9 of 9 (100 per page; Change: )
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