Search results for "CMOS circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
3	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
3	Mostafa H. Abd-El-Barr, Yanging Xu, Carl McCrosky	Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Transistor stuck-open fault, multi-level CMOS circuits testing, robust CMOS testing, test pattern generation, two-pattern test
3	Rosa Rodríguez-Montañés, Joan Figueras	Bridges in sequential CMOS circuits: current-voltage signatur.	VTS	1997	DBLP DOI BibTeX RDF	sequential CMOS circuits, current-voltage signature, I/sub DDQ/-V/sub DD/ signature, control loop nodes, fault diagnosis, fault diagnosis, temperature dependence, bridging defects
3	Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana	Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I/sub DDQ/ Testing in BiCMOS and CMOS Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	input pattern classification, BiCMOS circuits, quiescent power supply current monitoring, enhanced I/sub DDQ/, fault diagnosis, bridging faults, CMOS circuits, I/sub DDQ/ testing, stuck-ON faults
3	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
3	Beyin Chen, Chung-Len Lee	Universal test set generation for CMOS circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	functional testing, automatic test generation, CMOS circuits, stuck-open faults, universal test set
2	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
2	Ender Yilmaz, Günhan Dündar	Analog Layout Generator for CMOS Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
2	Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Ariana Filoramo, Christian Gamrat, Jean-Philippe Bourgoin	Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.	NanoNet	2009	DBLP DOI BibTeX RDF	Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
2	I-Chyn Wey, You-Gang Chen, An-Yeu Wu	Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu	Controllability of Static CMOS Circuits for Timing Characterization.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Design for test, Delay fault testing, Scan design
2	Paul G. A. Jespers	Sizing CMOS circuits by means of the gm/ID methodology and a compact model.	SBCCI	2008	DBLP DOI BibTeX RDF	circuit sizing
2	Enrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino	Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.	DSD	2008	DBLP DOI BibTeX RDF
2	Sudhakar M. Reddy, Irith Pomeranz, Chen Liu	On tests to detect via opens in digital CMOS circuits.	DAC	2008	DBLP DOI BibTeX RDF	constrained stuck-at tests, test generation, DFT, open defects
2	Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	José Ángel Díaz-Madrid, Pedro Monsalve-Campillo, Juan Hinojosa, María Victoria Rodellar Biarge, Ginés Doménech-Asensi	Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits.	IWINAC	2007	DBLP DOI BibTeX RDF
2	Bipul C. Paul, Kaushik Roy	Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	adaptive body bias design, statistical analysis, process variation, delay fault testing
2	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	Test Generation for Open Defects in CMOS Circuits.	DFT	2006	DBLP DOI BibTeX RDF
2	Walid Elgharbawy, Pradeep Golconda, Ashok Kumar, Magdy Bayoumi	A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Bipul Chandra Paul, Cassondra Neau, Kaushik Roy	Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.	ITC	2004	DBLP DOI BibTeX RDF
2	Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín	Techniques for very low-voltage operation of continuous-time analog CMOS circuits.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Narender Hanchate, Nagarajan Ranganathan	A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Najwa Aaraj, Anis Nazer, Ali Chehab, Ayman I. Kayssi	Transient Current Testing of Dynamic CMOS Circuits.	DFT	2004	DBLP DOI BibTeX RDF
2	Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim	Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
2	Rafik S. Guindi, Farid N. Najm	Design Techniques for Gate-Leakage Reduction in CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
2	Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez	Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Kaushik Roy, T. M. Mak, Kwang-Ting Cheng	Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits.	VTS	2003	DBLP DOI BibTeX RDF
2	Debasis Samanta, Ajit Pal	Synthesis of Dual-VT Dynamic CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF	nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT
2	Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali	Least-square estimation of average power in digital CMOS circuits.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
2	Yukiya Miura, Shuichi Seno	Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	fault behavior, feedback bridging faults, IDDQ testing, CMOS circuits, fault analysis
2	Alice Wang, Anantha Chandrakasan, Stephen V. Kosonocky	Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits.	ISVLSI	2002	DBLP DOI BibTeX RDF
2	Bassam Shaer, Khaled Dib	An Efficient Partitioning Algorithm of Combinational CMOS Circuits.	ISVLSI	2002	DBLP DOI BibTeX RDF	partitioning, pseudoexhaustive testing
2	Artur Wróblewski, Florian Auernhammer, Josef A. Nossek	Minimizing Spurious Switching Activities in CMOS Circuits.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita	Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Clock-delayed domino circuit, Fault simulation, crosstalk fault
2	Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min	Test Power Optimization Techniques for CMOS Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
2	Debasis Samanta, Nishant Sinha, Ajit Pal	Synthesis of High Performance Low Power Dynamic CMOS Circuits.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Debasis Samanta, Ajit Pal	Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Massimo Conti, Paolo Crippa, Simone Orcioni, M. Pesare, Claudio Turchetti, Loris Vendrame, S. Lucherini	A new methodology for the statistical analysis of VLSI CMOS circuits and its application to flash memories.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer	Minimum-power retiming for dual-supply CMOS circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	dual-supply, retiming theory, low-power, synthesis, low-power design
2	Zhanping Chen, Liqiong Wei, Kaushik Roy	On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
2	Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali	Average Power in Digital CMOS Circuits using Least Square Estimation.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal	Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
2	Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia	Gate-level simulation of CMOS circuits using the IDDM model.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng	Estimation for maximum instantaneous current through supply lines for CMOS circuits.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
2	Zhanping Chen, Liqiong Wei, Kaushik Roy	On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.	ISQED	2000	DBLP DOI BibTeX RDF
2	Payam Heydari, Massoud Pedram	Analysis and Optimization of Ground Bounce in Digital CMOS Circuits. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
2	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
2	Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy	Models and algorithms for bounds on leakage in CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
2	Maitham Shams, Mohamed I. Elmasry	A formulation for quick evaluation and optimization of digital CMOS circuits.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Hormoz Djahanshahi, C. Andre T. Salama	Differential 0.35µm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Qi Wang, Sarma B. K. Vrudhula	An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits.	ICCD	1999	DBLP DOI BibTeX RDF	low power, CMOS circuits, dual Vt
2	Takahiro Hozumi, Osamu Kakusho, Yutaka Hata	The Output Permutation for the Multiple-Valued Logic Minimization with Universal Literals. (PDF / PS)	ISMVL	1999	DBLP DOI BibTeX RDF	universal literal, output permutation, current-mode CMOS circuits, logic synthesis, cost reduction
2	Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen	Efficient timing analysis for CMOS circuits considering data dependent delays.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy	IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	IDD Waveforms Analysis, Testing
2	Yi-Min Jiang, Kwang-Ting Cheng	Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits.	DATE	1998	DBLP DOI BibTeX RDF
2	Dhamin Al-Khalili, Saman Adham, Come Rozon, Moazzem Hossain, D. Racz	Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	CMOS Defect Modeling, Defect Analysis
2	Uwe Hübner, Heinrich Theodor Vierhaus, Raul Camposano	Partitioning and analysis of static digital CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
2	Xunwei Wu, Massoud Pedram	Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	MVL, ternary circuit, current-mode circuit, CCD
2	Salvador Manich, Joan Figueras	Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.	ED&TC	1997	DBLP DOI BibTeX RDF
2	Chuan-Yu Wang, Kaushik Roy	COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	CMOS Digital Circuits, Reliability, Power Estimation
2	Zhanping Chen, Kaushik Roy, Tan-Li Chou	Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.	ICCAD	1997	DBLP DOI BibTeX RDF	Monte Carlo based approach, maximum bounds, minimum bounds, power dissipation estimation, power sensitivity, primary inputs, signal properties, signal switching, uncertain specifications, logic CAD, CMOS logic circuits, power estimation, CMOS circuits, signal probability, statistical technique
2	Manjit Borah, Robert Michael Owens, Mary Jane Irwin	Transistor sizing for low power CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
2	Razak Hossain, Menghui Zheng, Alexander Albicki	Reducing power dissipation in CMOS circuits by signal probability based transistor reordering.	IEEE Trans. on CAD of Integrated Circuits and Systems	1996	DBLP DOI BibTeX RDF
2	Chuan-Yu Wang, Kaushik Roy	Maximum power estimation for CMOS circuits using deterministic and statistic approaches.	VLSI Design	1996	DBLP DOI BibTeX RDF	maximum power estimation, deterministic approach, instantaneous power consumption, ATG technique, Monte Carlo based technique, computational complexity, VLSI, lower bound, statistical analysis, automatic testing, circuit analysis computing, Monte Carlo methods, automatic test generation, VLSI circuits, CMOS circuits, CMOS digital integrated circuits, statistic approach
2	Massoud Pedram	Power minimization in IC design: principles and applications.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	adiabatic circuits, dynamic power dissipation, low power layout, low power synthesis, lower-power design, power analysis and estimation, power minimization and management, silicon-on-insulator technology, switched capacitance, synthesis, system design, power management, layout, probabilistic analysis, symbolic simulation, CMOS circuits, switching activity, statistical sampling, computer-aided design of VLSI, gated clocks, energy-delay product
2	Yuyun Liao, D. M. H. Walker	Optimal voltage testing for physically-based faults.	VTS	1996	DBLP DOI BibTeX RDF	optimal voltage testing, physically-based faults, resistive bridges, gate outputs, pattern sensitive functional faults, transmission gates, fault diagnosis, logic testing, delays, integrated circuit testing, automatic testing, fault coverage, CMOS logic circuits, delay faults, Iddq tests, CMOS circuits, logic gates, test vector, noise margin, selection strategy, low-voltage testing, integrated circuit noise
2	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
2	Keivan Navi, Daniel Etiemble	From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multivalued current mode CMOS circuits, voltage mode CMOS arithmetic operators, 3-valued current mode CMOS 2-input BSC adder, CMOS binary 4-2 counter, 1-digit Avizienis-like adder, adders, CMOS integrated circuits, integrated logic circuits, multivalued logic circuits, ternary logic, redundant number representation
2	Josep Rius, Joan Figueras	Detecting I/sub DDQ/ defective CMOS circuits by depowering.	VTS	1995	DBLP DOI BibTeX RDF	I/sub DDQ/ defective CMOS circuits, depowering, fault detection capabilities, quiescent state, logic valves, discharge current, power supply line disconnection, logic testing, integrated circuit testing, fault location, CMOS logic circuits, capacitance
2	A. K. B. A'ain, A. H. Bratt, A. P. Dorey	Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing technique.	VLSI Design	1995	DBLP DOI BibTeX RDF	analogue CMOS circuits, power supply voltage control testing technique, floating gate defect exposure, power supply voltage sweep, fault diagnosis, integrated circuit testing, fault detection, fault coverage, integrated circuit modelling, CMOS analogue integrated circuits
2	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
2	Sasan Iman, Massoud Pedram	Two-level logic minimization for low power.	ICCAD	1995	DBLP DOI BibTeX RDF	Power Prime Implicants, low power two-level logic minimization, minimum covering problem, minimum power solution, static CMOS circuits, logic design, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, circuit optimisation, minimisation of switching nets
2	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
2	S. G. Younis, Thomas F. Knight Jr.	Non-dissipative rail drivers for adiabatic circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics
2	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
2	Chuan-Yu Wang, Kaushik Roy	Control unit synthesis targeting low-power processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming
2	S. Wayne Bollinger, Scott F. Midkiff	Test generation for IDDQ testing of bridging faults in CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Hong Hao, Edward J. McCluskey	Analysis of Gate Oxide Shorts in CMOS Circuits.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	resistance dependence, voltage dependence, pattern dependence, logic gate operation, p-channel transistors, n-channel transistors, CMOS integrated circuits, integrated logic circuits, CMOS circuits, logic gates, defect models, temperature dependence, gate oxide shorts, semiconductor device models
2	Michele Favalli, Piero Olivo, Bruno Riccò	A probabilistic fault model for `analog' faults in digital CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1992	DBLP DOI BibTeX RDF
2	Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò	Fault simulation of unconventional faults in CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
2	H. Y. Chen, Sung-Mo Kang	A new circuit optimization technique for high performance CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
2	Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski	A new algorithm for transistor sizing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF
2	Rene David, S. Rahal, J. L. Rainard	Some relationships between delay testing and stuck-open testing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF	stuck-open, combinational circuits, CMOS, Delay testing, robust test
2	Gopal Gupta, Niraj K. Jha	A universal test set for CMOS circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF
2	Lynne Michelle Brocco, Steven Paul McCormick, Jonathan Allen	Macromodeling CMOS circuits for timing simulation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF
1	Michael B. Henry, Leyla Nazhandali	From Transistors to NEMS: Highly Efficient Power-Gating of CMOS Circuits.	JETC	2012	DBLP DOI BibTeX RDF
1	Maurice Meijer, José Pineda de Gyvez	Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Georgios Panagopoulos, Charles Augustine, Kaushik Roy	A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach.	DATE	2012	DBLP BibTeX RDF
1	Kodai Kikuchi, Fanghua Pu, Hiroshi Yamauchi, Masaaki Iizuka, Masakazu Nakamura, Kazuhiro Kudo	CMOS Circuits Based on a Stacked Structure Using Silicone-Resin as Dielectric Layers.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Wolfgang Mathis, Jan-K. Bremer	Design of nonlinear CMOS circuits in the Nano-GHz Era and its mathematical challenges.	Mathematics and Computers in Simulation	2011	DBLP DOI BibTeX RDF
1	Jinhui Wang, Na Gong, Ligang Hou, Xiaohong Peng, Ramalingam Sridhar, Wuchen Wu	Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations.	Microelectronics Reliability	2011	DBLP DOI BibTeX RDF
1	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar	Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Delay optimization considering power saving in dynamic CMOS circuits.	ISQED	2011	DBLP DOI BibTeX RDF
1	Ganesh C. Patil, S. Qureshi	Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Michal Bryk, Lech Józwiak, Wieslaw Kuzmicz	Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits.	DSD	2011	DBLP DOI BibTeX RDF
1	Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu	Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Stéphane Burignat, Michael Kirkedal Thomsen, Michal Klimczak, Mariusz Olczak, Alexis De Vos	Interfacing Reversible Pass-Transistor CMOS Chips with Conventional Restoring CMOS Circuits.	RC	2011	DBLP DOI BibTeX RDF