Search results for "CMOS technology"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Ru Huang, HanMing Wu, Jinfeng Kang, DeYuan Xiao, XueLong Shi, Xia An, Yu Tian, Runsheng Wang, Liangliang Zhang, Xing Zhang, Yangyuan Wang	Challenges of 22 nm and beyond CMOS technology.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	22 nm technology node, device architectures, metal gate/high K dielectrics, ultra low K dielectrics, CMOS technology
3	Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh	A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology.	VLSI Design	1995	DBLP DOI BibTeX RDF	integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation
2	Samar K. Saha	Modeling Process Variability in Scaled CMOS Technology.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	compact variability modeling, gate-oxide thickness variability, high-k dielectric, line-edge roughness, polysilicon granularity, random discrete dopants, scaled CMOS technology, statistical compact modeling, design and test, process variability, metal gate
2		Compact variability modeling to the rescue.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	compact variability modeling, nanometer CMOS technology, CMOS technology, design and test
2	Soheil Ziabakhsh, Hosein Alavi-Rad, Mohammad Alavi-Rad, Mohammad Mortazavi	The design of a low-power high-speed current comparator in 0.35-m CMOS technology.	ISQED	2009	DBLP DOI BibTeX RDF
2	Luiz Carlos Moreira, Wilhelmus A. M. Van Noije, Armando Ayala Pabón, Andrés Farfán-Peláez	Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology.	SBCCI	2009	DBLP DOI BibTeX RDF	cross inductors, rectangular inductors, RF CMOS
2	Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz	MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.	DDECS	2009	DBLP DOI BibTeX RDF
2	Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz	Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS.	DDECS	2009	DBLP DOI BibTeX RDF
2	Yangyuan Wang, Xing Zhang, Xiaoyan Liu, Ru Huang	Novel devices and process for 32 nm CMOS technology and beyond.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	high-k, non-planar MOSFET, quasi-ballistic transport, CMOS technology, metal gate
2	Nathalie Deltimple, Yann Deval, Didier Belot, Eric Kerherve	Design of Class-E power VCO in 65nm CMOS technology: Application to RF transmitter architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Stefano Ruzza, Enrico Dallago, Giuseppe Venchi, Sergio Morini	An offset compensation technique for bandgap voltage reference in CMOS technology.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Kurt Schweiger, Horst Zimmermann	Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology.	DDECS	2008	DBLP DOI BibTeX RDF
2	Wei-Zen Chen, Da-Shin Lin	A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
2	Riaz Naseer, Jeff Draper, Younes Boulghassoul, Sandeepan DasGupta, Art Witulski	Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	critical charge, soft error, single event transient
2	Miriam Adlerstein Marwick, Andreas G. Andreou	Fabrication and Testing of Single Photon Avalanche Detectors in the TSMC 0.18µm CMOS Technology.	CISS	2007	DBLP DOI BibTeX RDF
2	Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera	A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology.	ASP-DAC	2007	DBLP DOI BibTeX RDF	on-chip signaling circuit, impedance-unmatched CML driver, differential transmission-line, CML receiver, CML buffer, load resistance tuning, 10 Gbit/s, CMOS technology, power reduction, 90 nm
2	Ming-Dou Ker, Hung-Tai Liao	Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Franklin Bien, Soumya Chandramouli, Hyoungsoo Kim, Edward Gebara, Joy Laskar	Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Tien-Yu Lo, Chung-Chih Hung	1-V Linear CMOS Transconductor with 65 dB THD in Nano-Scale CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Muhammad Usama, Tad A. Kwasniewski	A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi	Low-Power High-Speed 180-nm CMOS Clock Drivers.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.640 ns, CMOS clock drivers, register array, delay flip-flops, 251 muW, CMOS technology, power dissipation, delay time, 0.18 micron
2	Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu	A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces.	ASP-DAC	2007	DBLP DOI BibTeX RDF	Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron
2	Ivan C. H. Ivan Chee Hong Lai, M. Fujishima	Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar Systems.	ASP-DAC	2007	DBLP DOI BibTeX RDF	1.2 V, pseudomillimeter-wave up-conversion mixer, vehicular radar systems, broadband up-conversion mixer, on-chip Marchand baluns, reduced substrate losses, integrated mixer, 20 to 26 GHz, 2 dB, 11.1 mW, CMOS technology, capacitive coupling, 90 nm
2	Shin-Yi Lin, Chih-Tsun Huang	A High-Throughput Low-Power AES Cipher for Network Applications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, low-power AES cipher, two-stage pipeline, CCM mode, design-for-test circuitry, 4.27 Gbits/s, 333 MHz, 40.9 mW, CMOS technology, network applications
2	M. Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Begueret	A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-in current sensor
2	Tai-Xiang Lai, Ming-Dou Ker	Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology.	ISQED	2006	DBLP DOI BibTeX RDF
2	Hsin-Chyh Hsu, Ming-Dou Ker	Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask.	ISQED	2006	DBLP DOI BibTeX RDF
2	Xiongfei Meng, Resve A. Saleh, Karim Arabi	Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology.	ISQED	2006	DBLP DOI BibTeX RDF
2	Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai	A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Tung N. Pham, Earl E. Swartzlander Jr.	Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology.	ASAP	2006	DBLP DOI BibTeX RDF
2	Fatemeh Aezinia, Behjat Forouzandeh	A Novel Low Power NOR gate in SOI CMOS Technology.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Ryan Bespalko, Brian Frank	Analysis and Design of a 10 Gbps Transimpedance Amplifier using 0.18µm CMOS technology.	CCECE	2006	DBLP DOI BibTeX RDF
2	Niladri Roy, Mani Najmabadi, Rabin Raut, Vijay Kumar Devabhaktuni	A Systematic Approach Towards the Implementation of a Low-Noise Amplifier in Sub-Micron CMOS Technology.	CCECE	2006	DBLP DOI BibTeX RDF
2	A. Motieifar, Zahra Allahgholi Pour, G. Bridges, C. Shafai, L. Shafai	An Ultra Wideband (UWB) Mixer with 0.18µm RF CMOS Technology.	CCECE	2006	DBLP DOI BibTeX RDF
2	Cristiano Niclass, Maximilian Sergio, Edoardo Charbon	A single photon avalanche diode array fabricated in deep-submicron CMOS technology.	DATE	2006	DBLP DOI BibTeX RDF
2	Jordan Lai	SRAM Design Techniques for Sub-nano CMOS Technology.	MTDT	2006	DBLP DOI BibTeX RDF
2	M. Cimino, Hervé Lapuyade, M. De Matos, Thierry Taris, Yann Deval, Jean-Baptiste Begueret	A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications.	European Test Symposium	2006	DBLP DOI BibTeX RDF	Analog and mixed-signal integrated circuits, Robustness, Design for testability, CMOS technology, Built-In current sensor
2	Bhaskar Chatterjee, Manoj Sachdev	Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Haigang Yang, Hongguang Sun, Jinghong Han, Jinbao Wei, Zengjin Lin, Shanhong Xia, Hua Zhong	A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology.	IWSOC	2005	DBLP DOI BibTeX RDF	Micro Sensor System, ISFET, CMOS, SOC
2	Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao	A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, Min Hao	Standard CMOS technology on-chip inductors with pn junctions substrate isolation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Fabrizio De Nisi, David Stoppa, Mauro Scandiuzzo, Lorenzo Gonzo, Lucio Pancheri, Gian-Franco Dalla Betta	Design of electro-optical demodulating pixel in CMOS technology.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Manuel Delgado-Restituto, Jesús Ruiz-Amaya, José Manuel de la Rosa, Juan Francisco Fernández-Bootello, Leila Díez, Rocío del Río Fernández, Ángel Rodríguez-Vázquez	An embedded 12-bit 80MS/s A/D/A interface for power-line communications in 0.13µm pure digital CMOS technology.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen	Architecture for area-efficient 2-D transform in H.264/AVC.	ICME	2005	DBLP DOI BibTeX RDF	architecture shrinking, 2-D transform, H.264-AVC, automatic volume control, very large scale integration, ASIC, application-specific integrated circuit, matrix multiplication, minimization, CMOS technology, VLSI technology
2	Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije	A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology.	SBCCI	2004	DBLP DOI BibTeX RDF	TSPC, high speed digital circuit, low power, prescaler
2	Iman Y. Taha, Majid Ahmadi, William C. Miller	A Sigma-Delta Modulator for Digital Hearing Instruments Using 0.18µm CMOS Technology.	IWSOC	2004	DBLP DOI BibTeX RDF
2	Keiichiro Kagawa, Tomoaki Kawakami, Hiroaki Asazu, Takashi Ikeuchi, Akiko Fujiuchi, Jun Ohta, Masahiro Nunoshita	An image-sensor-based optical receiver fabricated in a standard 0.35-µm CMOS technology for free-space optical communications.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Chung-Wei Lin, Yen-Zen Liu, Klaus Y. J. Hsu	A low distortion and fast settling automatic gain control amplifier in CMOS technology.	ISCAS	2004	DBLP DOI BibTeX RDF
2	Tajeshwar Singh, Trond Ytterdal	A single-ended to differential capacitive sensor interface circuit designed in CMOS technology.	ISCAS	2004	DBLP DOI BibTeX RDF
2	Arif A. Siddiqi, Tad A. Kwasniewski	2.4 GHz RF down-conversion mixers in standard CMOS technology.	ISCAS	2004	DBLP DOI BibTeX RDF
2	H. C. Srinivasaiah, Navakanta Bhat	Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment.	VLSI Design	2004	DBLP DOI BibTeX RDF	Disposable spacer, Transmission of moments technique, Plackett-Burman design, Sensitivity analysis, Statistical modeling, CMOS technology, Response surface methodology, Monte carlo analysis
2	Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner	A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate.	ISLPED	2003	DBLP DOI BibTeX RDF	SOI CMOS, high resistivity substrate, phase NoiseFOM, low power, VCO, RF design
2	Ertan Zencir, Numan Sadi Dogan, Ercument Arvas, Mohammed Ketel	A low-power low-noise amplifier in 0.35µm SOI CMOS technology.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Andrea Maniero, Andrea Gerosa, Andrea Neviani	Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Zeynep Toprak Deniz, Yusuf Leblebici	Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Andrea Gerosa, Andrea Neviani	A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Koichi Nose, Takayasu Sakurai	Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.	ISLPED	2002	DBLP DOI BibTeX RDF
2	Sandro A. P. Haddad, Wouter A. Serdijn	High-frequency dynamic translinear and log-domain circuits in CMOS technology.	ISCAS	2002	DBLP DOI BibTeX RDF
2	E. Shen, J. B. Kuo	0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems.	ISCAS	2002	DBLP DOI BibTeX RDF
2	T. Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond	Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).	MTDT	2002	DBLP DOI BibTeX RDF
2	T. Suutari, Jouni Isoaho, Hannu Tenhunen	High-speed serial communication with error correction using 0.25 um CMOS technology.	ISCAS	2001	DBLP DOI BibTeX RDF
2	George Gristede, Wei Hwang	A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
2	V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, J. Ashley, R. Karabed	A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder.	ASAP	2000	DBLP DOI BibTeX RDF	disk-drive read channels, high-speed Viterbi decoder, radix-4 add-compare-select, bit-level pipelining, full-custom macros, datapath generator assisted design, 0.25 micron, 550 MHz, CMOS technology, redundant number representations
2	Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou	etection of SRAM cell stability by lowering array supply voltage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	SRAM cell stability detection, array supply voltage reduction, design-for-test technique, static random access memory, memory array, test mode, detection capability, logic testing, integrated circuit testing, design for testability, CMOS technology, SRAM chips, CMOS memory circuits, DFT technique, circuit stability, 0.18 micron
2	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
2	Eugeni García-Moreno, Benjamín Iñíguez, Miquel Roca, Jaume Segura, Eugeni Isern	Clocked Dosimeter Compatible with Digital CMOS Technology.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	radiation dosimeter, radiation effects, digital circuits, CMOS technology
2	B. Chester Hwang	Trends of Key Advanced Device Technologies.	ARVLSI	1997	DBLP DOI BibTeX RDF	SIA roadmap, Sematech, TFSOI, graded-channel CMOS, complementary IC technology, 0.25 micron, CMOS integrated circuits, CMOS technology, Moore's law, GaAs, Si
2	Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele	A flexible VLSI architecture for variable block size segment matching with luminance correction.	ASAP	1997	DBLP DOI BibTeX RDF	flexible VLSI architecture, variable block size segment matching, luminance correction, segment matching VLSI architecture, evolving motion estimation algorithms, preprocessing unit, halfpel interpolation, pixel decimation, VHDL synthesis, VLSI, CMOS technology, motion vectors, RAM, block matching algorithms, video coding standards
2	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
2	Yinan N. Shen, Xiao-Tao Chen, Susumu Horiguchi, Fabrizio Lombardi	On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model. (PDF / PS)	ICPP	1997	DBLP DOI BibTeX RDF	CMOS fault model, multiple fault diagnosis, interconnection networks, fault diagnosis, lower bound, multistage interconnection networks, multistage interconnection networks, CMOS technology, stuck-open faults
2	Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An	A Scalable Memory System Design.	VLSI Design	1997	DBLP DOI BibTeX RDF	scalable memory system, pipeline technique, systolic data flow, sub-memory blocks, partial binary tree structure, multidirectional data flow, chip size, 4 kbit, 0.8 micron, 5.1 ns, 3.5 mm, throughput, latency, memory architecture, memory architecture, CMOS technology, communication channel, access time, operating speed, clock speed
2	Mostafa H. Abd-El-Barr, M. N. Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
2	Christian Piguet, T. Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers	Low-Power Embedded Microprocessor Design.	EUROMICRO	1996	DBLP DOI BibTeX RDF	low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles
2	Navin Chaddha, Mohan Vishwanath	A low power video encoder with power, memory and bandwidth scalability.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power video encoder, power scalability, memory scalability, bandwidth scalability, portable video, generic block transform, memory rate distortion, perceptually weighted hierarchical vector quantization, 150 to 300 W, 0.8 micron, 1.5 V, video coding, power consumption, transform coding, table lookup, table lookup, CMOS technology, vector quantisation, block codes
2	Debabrata Ghosh, S. K. Nandy	Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
2	Andreas G. Andreou, Kwabena Boahen	A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon retina, analog VLSI focal plane processor, phototransduction, local gain control, single chip system, vertebrate distal retina, ultra low power dissipation, n-well double metal double poly digital oriented CMOS technology, current-mode subthreshold CMOS, 48000 pixel, computer vision, VLSI, edge detection, CMOS integrated circuits, image sensors, contrast, edge enhancement, CMOS imager, focal planes, area efficiency, 1.2 micron
2	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
2	Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter	Combined DRAM and logic chip for massively parallel systems.	ARVLSI	1995	DBLP DOI BibTeX RDF	EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
2	Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III	A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.	ARVLSI	1995	DBLP DOI BibTeX RDF	high-speed fine-resolution pattern generation, data signals, edge placement, matched delays, MOSIS CMOS technology, 100 ps, 833 Mbit/s, architecture, delays, test pattern generators, network interfaces, CMOS digital integrated circuits, 1.2 micron
2	A. Agrawal, A. Raju, S. Varadarajan, Magdy A. Bayoumi	A scalable shared buffer ATM switch architecture.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	electronic switching systems, field effect transistor switches, scalable shared buffer ATM switch architecture, memory bandwidth requirement, maximum crosspoint switch size, buffer memory size, access time reduction, multiple buffer memories, 8/spl times/8 switch, 1 mum, 622 Mbit/s, asynchronous transfer mode, asynchronous transfer mode, shared memory systems, buffer storage, CMOS technology, CMOS digital integrated circuits, B-ISDN, B-ISDN, switching circuits, parallel access
2	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
2	Wai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau	Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	artificial satellites, smart-pixel array processors, optimal cellular neural networks, space sensor applications, hardware annealing, digitally programmable synaptic weights, multisensor parallel interface, programmable multi-dimensional array, optoelectronic neurons, neuroprocessor, scalable multiprocessor system, intelligent multisensor, advanced small satellites, neuroprocessor array chip, performance evaluation, real-time systems, parallel processing, CMOS technology, image sensors, aerospace computing, computing performance, neural chips, neural net architecture, intelligent sensors, active-pixel sensors, cellular neural nets
2	H. Yamada, T. Hotta, T. Nishiyama, F. Murabayashi, T. Yamauchi, H. Sawamoto	A 13.3ns double-precision floating-point ALU and multiplier. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit
2	K. Wayne Current	Memory Circuits for Multiple-Valued Logic Voltage Signals. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits
2	Vincenzo Catania, Marco Russo	Analog gates for a VLSI fuzzy processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI fuzzy processor, synchronous fuzzy circuits, high noise immunity, fuzzy gates, VLSI, fuzzy logic, CMOS logic circuits, CMOS technology, logic gates, analogue processing circuits
2	James Phillips, Stamatis Vassiliadis	High-Performance 3-1 Interlock Collapsing ALU's.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	3-1 interlock collapsing ALU, execution interlocks, multiple instruction issuing machines, parallel architectures, delay, digital arithmetic, CMOS technology, critical path, reduced instruction set computing, Boolean equations
2	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch	Fault modeling and fault equivalence in CMOS technology.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	test generation, Fault modeling, fault collapsing, fault equivalence
1	Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada	A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee	A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Daniel Fernández, Luís Martínez-Alvarado, Jordi Madrenas	A Translinear, Log-Domain FPAA on Standard CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung	A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Takeshi Ogawa, Toshiaki Edahiro, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Yuka Furuta, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Rieko Tanaka, Hiromitsu Komai, Mai Muramoto, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara	A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Raja Mahmou, Khalid Faitah	Designing of RF Single Balanced Mixer with a 65nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications	CoRR	2012	DBLP BibTeX RDF
1	Krit Salah-ddine, Zared Kamal, Qjidaa Hassan, Zouak Mohcine	A 100 mA Low Voltage Linear Regulators for Systems on Chip Applications Using 0.18 μm CMOS Technology	CoRR	2012	DBLP BibTeX RDF
1	Yunho Choi, Youngsu Kim, Huy Hoang, Franklin Bien	A 3.1-4.8-GHz IR-UWB All-Digital Pulse Generator With Variable Channel Selection in 0.13-µm CMOS Technology.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Chih-Ting Yeh, Ming-Dou Ker	New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu	Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application.	ISQED	2012	DBLP DOI BibTeX RDF
1	Haiqing Nan, Li Li, Ken Choi	TDDB-based performance variation of combinational logic in deeply scaled CMOS technology.	ISQED	2012	DBLP DOI BibTeX RDF
1	John F. Bulzacchelli, Troy J. Beukema, Daniel Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman	A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr	A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry.	ISSCC	2012	DBLP DOI BibTeX RDF