Search results for "Cache Memories"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino	Applying March Tests to K-Way Set-Associative Cache Memories.	European Test Symposium	2008	DBLP DOI BibTeX RDF	cache memories, memory test, march test
2	Salvador Petit, Noel Tomás, Julio Sahuquillo, Ana Pont	An execution-driven simulation tool for teaching cache memories in introductory computer organization courses.	WCAE	2006	DBLP DOI BibTeX RDF
2	Xavier Vera, Jaume Abella, Josep Llosa, Antonio González	An accurate cost model for guiding data locality transformations.	ACM Trans. Program. Lang. Syst.	2005	DBLP DOI BibTeX RDF	genetic algorithms, Cache memories, tiling, padding
2	Antonio Martí Campoy, Eugenio Tamura, S. Sáez, Francisco Rodríguez, José V. Busquets-Mataix	On Using Locking Caches in Embedded Real-Time Systems.	ICESS	2005	DBLP DOI BibTeX RDF	genetic algorithms, performance evaluation, predictability, response time, Cache memories, schedulability analysis, execution time, embedded real-time systems
2	Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González	A fast and accurate framework to analyze and optimize cache memory behavior.	ACM Trans. Program. Lang. Syst.	2004	DBLP DOI BibTeX RDF	optimization, sampling, Cache memories
2	Antonio Martí Campoy, S. Sáez, A. Perles, J. V. Busquets	Schedulability Analysis in EDF Scheduler with Cache Memories.	RTCSA	2003	DBLP DOI BibTeX RDF
2	Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike H. MacGregor	The Bank Nth Chance Replacement Policy for FPGA-Based CAMs.	FPL	2003	DBLP DOI BibTeX RDF	multizone cache, field programmable gate array, cache memories, memory systems, content addressable memories, replacement policy, digital design, Internet routing
2	Oleg Bessonov, Dominique Fougère, Bernard Roux	Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors.	PaCT	2003	DBLP DOI BibTeX RDF	linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors
2	Tohru Ishihara, Kunihiro Asada	An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories.	VLSI Design	2002	DBLP DOI BibTeX RDF
2	Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi	Let caches decay: reducing leakage energy via exploitation of cache generational behavior.	ACM Trans. Comput. Syst.	2002	DBLP DOI BibTeX RDF	generational behavior, Cache memories, leakage power, cache decay
2	Rita Cucchiara, Massimo Piccardi, Andrea Prati	Hardware Prefetching Techniques for Cache Memories in Multimedia Applications.	CAMP	2000	DBLP DOI BibTeX RDF	hardware prefetching, cache memory organization, multimedia image processing programs, MPEG-2 decoding, edge chain coding, image processing, multimedia, kernels, multimedia applications, cache memories
2	Jih-Kwon Peir, Windsor W. Hsu, Alan Jay Smith	Functional Implementation Techniques for CPU Cache Memories.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	cache access mechanism, cache area and bandwidth, Cache memory, address translation
2	Seongwoo Kim, Arun K. Somani	Area Efficient Architectures for Information Integrity in Cache Memories.	ISCA	1999	DBLP DOI BibTeX RDF
2	Philip P. Shirvani, Edward J. McCluskey	PADded Cache: A New Fault-Tolerance Technique for Cache Memories.	VTS	1999	DBLP DOI BibTeX RDF
2	Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam	Two Schemes to Improve the Performance of a Sort-Last 3D Parallel Rendering Machine with Texture Caches.	Euro-Par	1999	DBLP DOI BibTeX RDF	texture mapping, Cache memories, parallel rendering, multiprocessing, application specific architecture
2	José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings	Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems.	RTCSA	1996	DBLP DOI BibTeX RDF	harmonic task-sets, schedulable utilization, preemptive real-time systems, better performance, cache-related preemption cost, Response Time schedulability Analysis, real-time systems, cache memories, worst-case execution time, schedulability analysis
2	Krishna M. Kavi, Ali R. Hurson, Phenil Patadia, Elizabeth Abraham, Ponnarasu Shanmugam	Design of Cache Memories for Multi-Threaded Dataflow Architecture.	ISCA	1995	DBLP DOI BibTeX RDF
2	Cosimo Antonio Prete	Cachesim: A Graphical Software Environment to Support the Teaching of Computer Systems with Cache Memories.	CSEE	1994	DBLP DOI BibTeX RDF
2	Masaru Takesue	Cache Memories for Data Flow Machines.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	data flow machines, dataflow caches, cache block replacement, cache memories, memory architecture, buffer storage, register transfer level simulator
2	Dominique Thiébaut, Joel L. Wolf, Harold S. Stone	Synthetic Traces for Trace-Driven Simulation of Cache Memories.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	synthetic address traces, infinite address-space, synthetic traces, random walk, digital simulation, cache memories, memory architecture, trace-driven simulation, buffer storage, content-addressable storage
1	Krishna Kavi, Izuchukwu Nwachukwu, Ademola Fawibe	A comparative analysis of performance improvement schemes for cache memories.	Computers & Electrical Engineering	2012	DBLP DOI BibTeX RDF
1	Hyunjin Lee, Sangyeun Cho, Bruce R. Childers	DEFCAM: A design and evaluation framework for defect-tolerant cache memories.	TACO	2011	DBLP DOI BibTeX RDF
1	Stefano Di Carlo, Paolo Prinetto, Alessandro Savino	Software-Based Self-Test of Set-Associative Cache Memories.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Abel Guilhermino Silva-Filho, Filipe R. Cordeiro, Cristiano C. de Araujo, Sarmento Adriano, Millena Gomes, Edna Barros, Manoel Eusebio de Lima	An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms.	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	Izuchukwu Nwachukwu, Krishna Kavi, Fawibe Ademola, Chris Yan	Evaluation of Techniques to Improve Cache Access Uniformities.	ICPP	2011	DBLP DOI BibTeX RDF	Cache Indexing, Non-Uniformity of Cache Accesses, Cache Memories, Performance Improvement
1	Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy	Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura	Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo	Adaptive Cache Memories for SMT Processors.	DSD	2010	DBLP DOI BibTeX RDF
1	Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney	The Effect of Omitted-Variable Bias on the Evaluation of Compiler Optimizations.	IEEE Computer	2010	DBLP DOI BibTeX RDF	Omitted-variable bias, Cache memories, Design and test, Computer performance, Measurement errors
1	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures.	IEEE Micro	2010	DBLP DOI BibTeX RDF	nonuniform cache architectures, parallel architectures, multicore, cache memories, data placement
1	Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Making Address-Correlated Prefetching Practical.	IEEE Micro	2010	DBLP DOI BibTeX RDF	address-correlated prefetching, cache memories
1	Yiqiang Ding, Wei Zhang 0002	Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	cache memories, Real-time and embedded systems
1	Mohamed Zahran, Sally A. McKee	Global management of cache hierarchies.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	memory hierarchy, cache memory
1	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Aging effects of leakage optimizations for caches.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	memory hierarchy, aging, leakage reduction
1	Soontae Kim, Jongmin Lee 0002	Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low power, data cache, write buffer
1	Pedro Alonso, Raquel Cortina, Irene Díaz, José Ranilla	Blocking Neville elimination algorithm for exploiting cache memories.	Applied Mathematics and Computation	2009	DBLP DOI BibTeX RDF
1	Oluwayomi Adamo, Afrin Naz, Tommy Janjusic, Krishna M. Kavi, Chung-Ping Chung	Smaller Split L-1 Data Caches for Multi-core Processing Systems.	ISPAN	2009	DBLP DOI BibTeX RDF	Split data cache, uniform cache access patterns, Cache memories
1	Kapil Anand, Rajeev Barua	Instruction cache locking inside a binary rewriter.	CASES	2009	DBLP DOI BibTeX RDF	cache locking, embedded systems, caches, binary rewriting
1	Wei Zhang 0002	Computing and Minimizing Cache Vulnerability to Transient Errors.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Fadi N. Sibai	On the performance benefits of sharing and privatizing second and third-level cache memories in homogeneous multi-core architectures.	Microprocessors and Microsystems - Embedded Hardware Design	2008	DBLP DOI BibTeX RDF
1	Sung Jin Cho, Un-Sook Choi, Yoon-Hee Hwang, Han-Doo Kim	Design of new XOR-based hash functions for cache memories.	Computers & Mathematics with Applications	2008	DBLP DOI BibTeX RDF
1	Wilson J. Perez, Jaime Velasco-Medina, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda	Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs.	DDECS	2008	DBLP DOI BibTeX RDF
1	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
1	Luiza M. N. Coutinho, José Leandro D. Mendes, Carlos A. P. S. Martins	Dynamically Reconfigurable Split Cache Architecture.	ReConFig	2008	DBLP DOI BibTeX RDF	Computer Architecture, Reconfigurable Computing, Cache memories
1	Sung Woo Chung, Kevin Skadron	On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Low-power design, Microprocessors, Cache memories, Energy-aware systems
1	Mazen Kharbutli, Yan Solihin	Counter-Based Cache Replacement and Bypassing Algorithms.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Cache Bypassing, Counter-Based Algorithms, Cache memories, Cache Replacement, Cache Misses
1	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
1	Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim	A low-power phase change memory based hybrid cache architecture.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	PRAM, phase change memory
1	Roberto Giorgi, Paolo Bennati	Filtering drowsy instruction cache to achieve better efficiency.	SAC	2008	DBLP DOI BibTeX RDF	low-power, leakage, drowsy cache, filter cache
1	Mahdi Fazeli, Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi	A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors.	HASE	2008	DBLP DOI BibTeX RDF
1	Jie Tao, Asadollah Shahbahrami	Data Locality Optimization Based on Comprehensive Knowledge of the Cache Miss Reason: A Case Study with DWT.	HPCC	2008	DBLP DOI BibTeX RDF
1	Chih-Wen Hsueh, Jen-Feng Chung, Lan-Da Van, Chin-Teng Lin	Anticipatory access pipeline design for phased cache.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Yuh-Fang Tsai, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin	Design Space Exploration for 3-D Cache.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Filipe Oliveira, Castro M. P. Silva Santos, Fernando A. Castro, José Carlos Alves	A Custom Processor for a TDMA Solver in a CFD Application.	ARC	2008	DBLP DOI BibTeX RDF
1	Wei Zhang	Compiler-Assisted Leakage Energy Reduction for Cache Memories.	Advances in Computers	2007	DBLP DOI BibTeX RDF
1	Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura	Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories.	ESTImedia	2007	DBLP DOI BibTeX RDF
1	Yutao Zhong, Steven G. Dropsho, Xipeng Shen, Ahren Studer, Chen Ding	Miss Rate Prediction Across Program Inputs and Cache Configurations.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	optimization, compilers, Cache memories, modeling techniques, performance analysis and design aids
1	Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA Substrate for Flexible CMP Cache Sharing.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Multiprocessor systems, cache memories, adaptable architectures
1	Jaydeep Marathe, Frank Mueller	Source-Code-Correlated Cache Coherence Characterization of OpenMP Benchmarks.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	simulation, Cache memories, SMPs, program instrumentation, coherence protocols, dynamic binary rewriting
1	Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami	The effect of temperature on cache size tuning for low energy embedded systems.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	embedded systems, cache memory, low energy, leakage current, temperature-aware design
1	Sungjune Youn, Hyunhee Kim, Jihong Kim	A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.	ISLPED	2007	DBLP DOI BibTeX RDF	chip multiprocessors (CMPS), performance, embedded systems, architecture, low-power, L2 cache
1	Polychronis Koutsakis	Integrating latest technology multimedia traffic over high-speed cellular networks.	IWCMC	2007	DBLP DOI BibTeX RDF	multimedia traffic integration, cellular networks, MAC protocol
1	Ismail Kadayif, Mahmut T. Kandemir	Modeling and improving data cache reliability.	SIGMETRICS	2007	DBLP DOI BibTeX RDF	vulnerability factors, reliability, data integrity, soft errors, data caches
1	Xavier Vera, Björn Lisper, Jingling Xue	Data cache locking for tight timing calculations.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	data cache analysis, embedded systems, Worst-case execution time, safety critical systems
1	Wei Zhang 0002, Bramha Allu	Reducing branch predictor leakage energy by exploiting loops.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	compiler, Branch prediction, leakage energy
1	Polychronis Koutsakis	Resource Allocation for High Quality H.264 Streams Integrated with Web and MP3 Traffic over High-Speed Cellular Networks with Capture.	ICCCN	2007	DBLP DOI BibTeX RDF
1	Valentina Salapura, José R. Brunheroto, Fernando F. Redigolo, Alan Gara	Exploiting eDRAM bandwidth with data prefetching: simulation and measurements.	ICCD	2007	DBLP DOI BibTeX RDF
1	Polychronis Koutsakis	Bandwidth Allocation for Integrated MPEG-4 Video, WAP and MP3 Traffic over Next Generation Wireless Cellular Networks.	ICNS	2007	DBLP DOI BibTeX RDF
1	Kiyofumi Tanaka, Takenori Fujita	Leakage Energy Reduction in Cache Memory by Software Self-invalidation.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
1	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Adaptive L2 Cache for Chip Multiprocessors.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
1	Philipp Grabher, Johann Großschädl, Dan Page	Cryptographic Side-Channels from Low-Power Cache Memory.	IMA Int. Conf.	2007	DBLP DOI BibTeX RDF
1	Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato	A leakage-energy-reduction technique for cache memories in embedded processors.	J. Embedded Computing	2006	DBLP BibTeX RDF
1	Koji Inoue	Return Address Protection on Cache Memories.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Sung Jin Cho, Un-Sook Choi, Yoon-Hee Hwang, Han-Doo Kim	Modeling Efficient XOR-Based Hash Functions for Cache Memories.	International Conference on Computational Science	2006	DBLP DOI BibTeX RDF
1	Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	Leakage energy reduction techniques in deep submicron cache memories: a comparative study.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Jaume Abella, Antonio González	Heterogeneous way-size cache.	ICS	2006	DBLP DOI BibTeX RDF	adaptive, low power, cache memories, set-associative
1	Moon-Hee Choi, Woo-Chan Park, Francis Neelamkavil, Tack-Don Han, Shin-Dug Kim	An Effective Visibility Culling Method Based on Cache Block.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	visible/surface algorithms, Computer graphics, cache memories, graphics processors
1	Vilas Sridharan, Hossein Asadi, Mehdi Baradaran Tahoori, David R. Kaeli	Reducing Data Cache Susceptibility to Soft Errors.	IEEE Trans. Dependable Sec. Comput.	2006	DBLP DOI BibTeX RDF	refresh, refetch, Fault tolerance, reliability, cache memories, soft errors, error modeling
1	Hwansoo Han, Chau-Wen Tseng	Exploiting Locality for Irregular Scientific Codes.	IEEE Trans. Parallel Distrib. Syst.	2006	DBLP DOI BibTeX RDF	inspector/executor, data reordering, computation reordering, Compiler optimization, cache memories
1	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Evaluation of the field-programmable cache: performance and energy consumption.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	adaptive processors, reconfigurable cache memory, static and dynamic energy consumption, performance evaluation, run-time adaptation
1	Guilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Mustafa Karaköy	Dynamic scratch-pad memory management for irregular array access patterns.	DATE	2006	DBLP DOI BibTeX RDF
1	Erik Corry	Optimistic stack allocation for java-like languages.	ISMM	2006	DBLP DOI BibTeX RDF	stack allocation, Java, garbage collection
1	Leipo Yan, Siew Kei Lam, Thambipillai Srikanthan, Wu Jigang	Energy Efficient Cache Tuning with Performance Bound.	DELTA	2006	DBLP DOI BibTeX RDF
1	Isabelle Puaut	WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems.	ECRTS	2006	DBLP DOI BibTeX RDF
1	Polychronis Koutsakis	Efficient Wireless Bandwidth Allocation for MPEG-4 Videos Integrated with Web Traffic.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
1	Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu	Shared Scratch-Pad Memory Space Management.	ISQED	2006	DBLP DOI BibTeX RDF
1	Kugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke	Profile Directed Instruction Cache Tuning for Embedded Systems.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Shuai Wang, Jie S. Hu, Sotirios G. Ziavras	On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
1	Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López	Applying the zeros switch-off technique to reduce static energy in data caches.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
1	Yen-Jen Chang, Feipei Lai	Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Dynamic zero-sensitivity, Bitlines, DZS, Cache, Power reduction
1	Hamid R. Zarandi, Hamid Sarbazi-Azad	Hierarchical Binary Set Partitioning in Cache Memories.	The Journal of Supercomputing	2005	DBLP DOI BibTeX RDF
1	Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi	A Case for Asymmetric-Cell Cache Memories.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Hamid R. Zarandi, Seyed Ghassem Miremadi	Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme.	LADC	2005	DBLP DOI BibTeX RDF
1	Hamid R. Zarandi, Seyed Ghassem Miremadi	Hierarchical Multiple Associative Mapping in Cache Memories.	ECBS	2005	DBLP DOI BibTeX RDF
1	Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle	IATAC: a smart predictor to turn-off L2 cache lines.	TACO	2005	DBLP DOI BibTeX RDF	turning off cache lines, low power, Cache memories, L2 cache
1	Philip Jacob, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald	Predicting the Performance of a 3D Processor-Memory Chip Stack.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	Simulation, Cache memories, Performance of Systems
1	Cameron McNairy, Rohit Bhatia	Montecito: A Dual-Core, Dual-Thread Itanium Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability, Power Management, Cache memories, Multithreaded processors, Testing and Fault-Tolerance
1	Philip Machanick	The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	low-power design, cache memories, virtual memory, microkernels, main memory
1	Guangyu Chen, Mahmut T. Kandemir	Dataflow analysis for energy-efficient scratch-pad memory management.	ISLPED	2005	DBLP DOI BibTeX RDF	scratch pad memory (SPM), compiler, data flow analysis