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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10 occurrences of 8 keywords
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Results
Found 17 publication records. Showing 17 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Charles H. Stapper |
LSI yield modeling and process monitoring.  |
IBM Journal of Research and Development  |
2000 |
DBLP BibTeX RDF |
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| 1 | Wayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter |
Multipurpose DRAM architecture for optimal power, performance, and product flexibility. |
IBM Journal of Research and Development |
1995 |
DBLP BibTeX RDF |
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| 1 | Israel Koren, Zahava Koren, Charles H. Stapper |
A statistical study of defect maps of large area VLSI IC's. |
IEEE Trans. VLSI Syst. |
1994 |
DBLP DOI BibTeX RDF |
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| 1 | Charles H. Stapper, A. J. Rideout |
On Fractal Yield Models: A Statistical Paradox. |
DFT |
1994 |
DBLP BibTeX RDF |
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| 1 | Charles H. Stapper |
Improved Yield Models for Fault-Tolerant Memory Chips. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
fault-tolerant memory chips, defect-monitor data, redundant circuits, failure mechanisms, multivariate distributions, dynamic-random-access-memory, pragmatic approximation, fault tolerant computing, redundancy, DRAM chips, yield modeling, frequency distributions |
| 1 | Israel Koren, Zahava Koren, Charles H. Stapper |
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
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| 1 | Charles H. Stapper, J. A. Patrick, R. J. Rosner |
Yield Model for ASIC and Processor Chips. |
DFT |
1993 |
DBLP BibTeX RDF |
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| 1 | Charles H. Stapper, Hsing-San Lee |
Synergistic Fault-Tolerance for Memory Chips. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
bitline redundancy, memory chips, synergistic fault tolerance, VLSI memory chip, redundant circuits, wordline redundancy, fault-tolerance synergism, VLSI, fault tolerant computing, error-correcting codes, error correction codes, error-correction, DRAM chips |
| 1 | Charles H. Stapper |
A New Statistical Approach for Fault-Tolerant VLSI Systems. |
FTCS |
1992 |
DBLP DOI BibTeX RDF |
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| 1 | Charles H. Stapper |
Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1991 |
DBLP DOI BibTeX RDF |
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| 1 | Charles H. Stapper |
Simulation of spatial fault distributions for integrated circuit yield estimations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1989 |
DBLP DOI BibTeX RDF |
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| 1 | Charles H. Stapper |
Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review. |
IBM Journal of Research and Development |
1989 |
DBLP BibTeX RDF |
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| 1 | Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper |
Yield of VLSI circuits: myths vs. reality (panel). |
DAC |
1986 |
DBLP DOI BibTeX RDF |
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| 1 | Charles H. Stapper |
Modeling of Defects in Integrated Circuit Photolithographic Patterns. |
IBM Journal of Research and Development |
1984 |
DBLP BibTeX RDF |
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| 1 | Charles H. Stapper |
Yield Model for Fault Clusters Within Integrated Circuits. |
IBM Journal of Research and Development |
1984 |
DBLP BibTeX RDF |
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| 1 | Charles H. Stapper |
Modeling of Integrated Circuit Defect Sensitivities. |
IBM Journal of Research and Development |
1983 |
DBLP BibTeX RDF |
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| 1 | Charles H. Stapper |
LSI Yield Modeling and Process Monitoring. |
IBM Journal of Research and Development |
1976 |
DBLP BibTeX RDF |
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Displaying result #1 - #17 of 17 (100 per page; Change: )
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