| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert |
WRIP: logic restructuring techniques for wirelength-driven incremental placement.  |
ACM Great Lakes Symposium on VLSI  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji |
MAPLE: multilevel adaptive placement for mixed-size designs. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan |
Keep it straight: teaching placement how to better handle designs with datapaths. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan |
Shedding Physical Synthesis Area Bloat. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov |
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. |
IEEE Micro |
2011 |
DBLP DOI BibTeX RDF |
systems on chips, physical synthesis |
| 1 | Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr. |
Quantifying academic placer performance on custom designs. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy |
The ISPD-2011 routability-driven placement contest and benchmark suite. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | David A. Papa, Michael D. Moffitt, Charles J. Alpert, Igor L. Markov |
Speeding Up Physical Synthesis with Transactional Timing Analysis. |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo Tellez |
What makes a design difficult to route. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
congestion driven physical synthesis, routing |
| 1 | Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu |
ITOP: integrating timing optimization within placement. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
placement, timing optimization, physical synthesis |
| 1 | Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Ying Zhou |
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
gate duplication, physical synthesis, timing-driven placement |
| 1 | Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn |
Detecting tangled logic structures in VLSI netlists. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
congestion prediction, rent rule, tangled logic, clustering |
| 1 | Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan |
Design-hierarchy aware mixed-size placement for routability optimization. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Taraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew Huber, Shyam Ramji |
New placement prediction and mitigation techniques for local routing congestion. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiyan Hu, Zhuo Li, Charles J. Alpert |
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiyan Hu, Zhuo Li, Charles J. Alpert |
A faster approximation scheme for timing driven minimum cost layer assignment. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
dynamic programming, np-complete, oracle, fully polynomial time approximation scheme, layer assignment |
| 1 | Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert |
Ispd2009 clock network synthesis contest. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
benchmarks, physical design, vlsi, clock network synthesis |
| 1 | Shiyan Hu, Zhuo Li, Charles J. Alpert |
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
dynamic programming, NP-complete, buffer insertion, fully polynomial time approximation scheme, cost minimization |
| 1 | Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov |
CRISP: Congestion reduction by iterated spreading during placement. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov |
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov |
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
static timing analysis, timing-driven placement |
| 1 | Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia |
Fast interconnect synthesis with layer assignment. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
buffer insertion, wire sizing, layer assignment, interconnect synthesis |
| 1 | Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert |
Path smoothing via discrete optimization. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
static timing analysis, timing-driven placement |
| 1 | Tao Luo, David A. Papa, Zhuo Li, Chin-Ngai Sze, Charles J. Alpert, David Z. Pan |
Pyramids: an efficient computational geometry-based approach for timing-driven placement. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiyan Hu, Zhuo Li, Charles J. Alpert |
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam |
Diffusion-Based Placement Migration With Application on Legalization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze |
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
Path-Based Buffer Insertion. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi |
Probabilistic Congestion Prediction with Partial Blockages. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz |
The nuts and bolts of physical synthesis. |
SLIP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu |
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud |
Fast Electrical Correction Using Resizing and Buffering. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
electrical violation eliminator, fast electrical correction, electrical state |
| 1 | Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia |
Hippocrates: First-Do-No-Harm Detailed Placement. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
synthesis optimizations, Hippocrates, first-do-no-harm detailed placement, pin-based timing constraint, electrical constraints, reduced wire-length |
| 1 | Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia |
The coming of age of physical synthesis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng |
A Fast Hierarchical Quadratic Placement Algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
Accurate estimation of global buffer delay within a floorplan. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang |
Timing-driven Steiner trees are (practically) free. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
arborescence, timing-driven, rectilinear Steiner tree |
| 1 | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze |
Fast algorithms for slew constrained minimum cost buffering. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
slew constraint, physical design, buffer insertion |
| 1 | Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz |
The ISPD2005 placement contest and benchmark suite. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
VLSI placement, benchmarks, physical design |
| 1 | Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif |
An efficient surface-based low-power buffer insertion algorithm. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
low-power design, buffer insertion, physical synthesis |
| 1 | Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia |
A semi-persistent clustering technique for VLSI circuit placement. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
VLSI placement, physical design, hypergraph clustering |
| 1 | Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
Path based buffer insertion. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
layout, physical design, global routing, buffer insertion, power minimization, interconnect synthesis |
| 1 | Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia |
Diffusion-based placement migration. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
placement migration, diffusion, legalization |
| 1 | Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
Making fast buffer insertion even faster via approximation techniques. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz |
Placement stability metrics. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert |
Practical techniques to reduce skew and its variations in buffered clock networks. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan |
Computational geometry based placement migration. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay |
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert |
A delay metric for RC circuits based on the Weibull distribution. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan |
Closed-form delay and slew metrics made easy. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan |
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze |
Porosity-aware buffered Steiner tree construction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Milos Hrkic, Stephen T. Quay |
A fast algorithm for identifying good buffer insertion candidate locations. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
planning, global routing, buffer insertion, physical synthesis |
| 1 | Charles J. Alpert, Patrick Groeneveld (eds.) |
Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004 |
ISPD |
2004 |
DBLP BibTeX RDF |
|
| 1 | Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay |
Fast and flexible buffer trees that navigate the physical layout environment. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
global routing, buffer insertion, physical synthesis |
| 1 | Weiping Shi, Zhuo Li, Charles J. Alpert |
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Cliff C. N. Sze, Jiang Hu, Charles J. Alpert |
A place and route aware buffered Steiner tree construction. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
Accurate estimation of global buffer delay within a floorplan. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia |
Effective free space management for cut-based placement via analytical constraint generation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Soha Hassoun, Charles J. Alpert |
Optimal path routing in single- and multiple-clock domain systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Sachin S. Sapatnekar |
Guest editorial. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia |
A practical methodology for early buffer and wire resource allocation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham |
Buffer insertion with adaptive blockage avoidance. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky |
Minimum buffered routing with bounded capacitive load for slew rate and reliability control. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Massoud Pedram, Charles J. Alpert (eds.) |
Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003 |
ISPD |
2003 |
DBLP BibTeX RDF |
|
| 1 | Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay |
Porosity aware buffered steiner tree construction. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, physical design, buffer insertion |
| 1 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan |
Closed form expressions for extending step delay and slew metrics to ramp inputs. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
Elmore, slew, delay, timing, interconnects, PDF, moments, median, skewness |
| 1 | Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan |
Delay and slew metrics using the lognormal distribution. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay |
Correction to "interconnect synthesis without wire tapering". |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert |
Probability-driven routing in a datapath environment. |
Integration |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay |
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham |
Buffer insertion with adaptive blockage avoidance. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan |
PERI: a technique for extending delay and slew metrics to ramp inputs. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
Elmore, slew, delay, interconnects, PDF, moments, median, skewness, standard deviation |
| 1 | David P. LaPotin, Charles J. Alpert, John Lillis (eds.) |
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002 |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP BibTeX RDF |
|
| 1 | Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia |
Free space management for cut-based placement. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert |
A delay metric for RC circuits based on the Weibull distribution. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Soha Hassoun, Charles J. Alpert, Meera Thiagarajan |
Optimal buffered routing path constructions for single and multiple clock domain systems. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay |
Interconnect synthesis without wire tapering. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar |
Steiner tree optimization for buffers, blockages, and bays. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap |
RC delay metrics for performance optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia |
Buffered Steiner trees for difficult instances. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia |
A Practical Methodology for Early Buffer and Wire Resource Allocation. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar |
Steiner tree optimization for buffers. Blockages and bays. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky |
Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. |
ICCAD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
Hypergraph partitioning with fixed vertices [VLSI CAD]. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap |
A two moment RC delay metric for performance optimization. |
ISPD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert |
Datapath routing based on a decongestion metric. |
ISPD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan |
An "Effective" Capacitance Based Delay Metric for RC Interconnect. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay |
Buffer insertion for noise and delay optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Andrew B. Kahng, So-Zen Yao |
Spectral Partitioning with Multiple Eigenvectors. |
Discrete Applied Mathematics |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
Partitioning with terminals: a "new" problem and new benchmarks. |
ISPD |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay |
Buffer Insertion with Accurate Gate and Interconnect Delay Computation. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay |
Is wire tapering worthwhile? |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng |
Multilevel circuit partitioning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet |
Faster minimization of linear wirelength for global placement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert |
The ISPD98 circuit benchmark suite. |
ISPD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan, Stephen T. Quay |
Buffer Insertion for Noise and Delay Optimization. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis, gate-sizing, fanout optimization |
| 1 | Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan |
Faster minimization of linear wirelength for global placement. |
ISPD |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Anirudh Devgan |
Wire Segmenting for Improved Buffer Insertion. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan |
Quadratic Placement Revisited. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
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