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Publications of "Charles Thangaraj" ( http://dblp.L3S.de/Authors/Charles_Thangaraj )

  Author page on DBLP  Author page in RDF  Community of Charles Thangaraj in ASPL-2

Publication years (Num. hits)
2007 (1) 2008 (2) 2010 (2)
Publication types (Num. hits)
article(2) inproceedings(3)
Venues (Conferences, Journals, ...)
DELTA(1) IEEE Trans. VLSI Syst.(1) Integration(1) ISCAS(1) ISVLSI(1)
Authors
Charles Thangaraj(5) Tom Chen(5) Alkan Cengiz(1) Guangwei Yuan(1) Kevin L. Lear(1) Phil Nikkel(1) Robert Pownall(1)
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Results
Found 5 publication records. Showing 5 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Charles Thangaraj, Robert Pownall, Phil Nikkel, Guangwei Yuan, Kevin L. Lear, Tom Chen Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Charles Thangaraj, Alkan Cengiz, Tom Chen Rapid design space exploration using legacy design data and technology scaling trend. Search on Bibsonomy Integration The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Charles Thangaraj, Tom Chen Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF pareto-front, What-if analysis, Power-performance trade-off
1Charles Thangaraj, Tom Chen Design target exploration for meeting time-to-market using pareto analysis. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Charles Thangaraj, Tom Chen Power andPerformance Analysis for Early Design Space Exploration. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Power-performance tradeoff, What-if analysis
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