Search results for "Cheng-Hung Lin"

Found 18 publication records. Showing 18 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang, Wing-Kai Hon	Memory-efficient pattern matching architectures using perfect hashing on graphic processing units.	INFOCOM	2012	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu	Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Shih-Chieh Chang	Efficient Pattern Matching Algorithm for Memory Architecture.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang	Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU.	GLOBECOM	2011	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Sheng-Yu Tsai, Chen-Hsiung Liu, Shih-Chieh Chang, Jyuo-Min Shyu	Accelerating String Matching Using Multi-Threaded Algorithm on GPU.	GLOBECOM	2010	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Chun-Yu Chen, Tsung-Han Tsai, An-Yeu Wu	Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Hsien-Sheng Hsiao	Hierarchical state machine architecture for regular expression pattern matching.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	pattern matching, regular expression, state machine
1	Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu	A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu	Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Chun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu	High-throughput dual-mode single/double binary map processor design for wireless wan.	SiPS	2008	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu	Low-power traceback MAP decoding for double-binary convolutional turbo decoder.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang	Optimization of Pattern Matching Circuits for Regular Expression on FPGA.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho	Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.	ISQED	2007	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang	Optimization of pattern matching algorithm for memory based architecture.	ANCS	2007	DBLP DOI BibTeX RDF	intrusion detection, pattern matching, DFA
1	Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu	A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold.	SiPS	2006	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang	Optimization of regular expression pattern matching circuits on FPGA.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone	Design and design automation of rectification logic for engineering change.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu	A memory-reduced log-MAP kernel for turbo decoder.	ISCAS	2005	DBLP DOI BibTeX RDF

Publications of "Cheng-Hung Lin" ( http://dblp.L3S.de/Authors/Cheng-Hung_Lin )