| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Stephen Cauley, Venkataramanan Balakrishnan, Gerhard Klimeck, Cheng-Kok Koh |
A two-dimensional domain decomposition technique for the simulation of quantum-scale devices.  |
J. Comput. Physics  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jongwon Lee, Duo Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Dan Jiao |
A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Guoyong Shi, Grantham K. H. Pang, Ngai Wong |
Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Hu, Cheng-Kok Koh |
Guest Editorial Special Section on the 2011 International Symposium on Physical Design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiang Hu, Cheng-Kok Koh (eds.) |
International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012 |
ISPD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |
A size scaling approach for mixed-size placement. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuai Li, Cheng-Kok Koh |
Mixed integer programming models for detailed placement. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Cauley, Venkataramanan Balakrishnan, Y. Charlie Hu, Cheng-Kok Koh |
A parallel branch-and-cut approach for detailed placement. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh |
Processor caches with multi-level spin-transfer torque ram cells. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 1 | Shashank Bujimalla, Cheng-Kok Koh |
Synthesis of low power clock trees for handling power-supply variations. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tarun Mittal, Cheng-Kok Koh |
Cross link insertion for improving tolerance to variations in clock network synthesis. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao |
Simultaneous redundant via insertion and line end extension for yield optimization. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao |
Optimal Double Via Insertion With On-Track Preference. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Cauley, Venkataramanan Balakrishnan, Cheng-Kok Koh |
A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy |
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ao-Jan Su, Y. Charlie Hu, Aleksandar Kuzmanovic, Cheng-Kok Koh |
How to Improve Your Google Ranking: Myths and Reality. |
Web Intelligence |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K. H. Pang, Ngai Wong |
PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li |
Tolerating process variations in large, set-associative caches: The buddy cache. |
TACO |
2009 |
DBLP DOI BibTeX RDF |
caches, Processor architectures, fault recovery, memory structures |
| 1 | Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh |
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenwen Chai, Dan Jiao, Cheng-Kok Koh |
A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
full wave, integral-equation-based methods, capacitance extraction, direct solver |
| 1 | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |
A study of routability estimation and clustering in placement. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li |
The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao |
Fast and Optimal Redundant Via Insertion. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao |
Optimal post-routing redundant via insertion. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
redundant via insertion, via density, integer linear program |
| 1 | Jitesh Jain, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan |
A fast band matching technique for impedance extraction. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan |
Guiding global placement with wire density. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden |
Routability-Driven Placement and White Space Allocation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruibing Lu, Aiqun Cao, Cheng-Kok Koh |
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong Li, Jitesh Jain, Venkataramanan Balakrishnan, Cheng-Kok Koh |
Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen Li 0004, Cheng-Kok Koh |
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen |
Statistical Timing Analysis Considering Spatial Correlations. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh |
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
variable-latency adder (VL-adder), negative bias temperature instability (NBTI) |
| 1 | Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan |
A fast band-matching technique for interconnect inductance modeling. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruilin Wang, Cheng-Kok Koh |
A frequency-domain technique for statistical timing analysis of clock meshes. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li |
VOSCH: Voltage scaled cache hierarchies. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiqun Cao, Ruibing Lu, Chen Li 0004, Cheng-Kok Koh |
Postlayout optimization for synthesis of Domino circuits. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
optimization, synthesis, Domino logic |
| 1 | Ruibing Lu, Cheng-Kok Koh |
Performance analysis of latency-insensitive systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, T.-S. Ng |
Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan |
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan |
Adaptive admittance-based conductor meshing for interconnect analysis. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh |
Stable and compact inductance modeling of 3-D interconnect structures. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy |
Synthesis of skewed logic circuits. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
Skewed logic, optimization, synthesis, power |
| 1 | Ameya R. Agnihotri, Satoshi Ono, Chen Li 0004, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Patrick H. Madden |
Mixed block placement via fractional cut recursive bisection. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh |
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
low-power, carry-select adder |
| 1 | Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh |
3D module placement for congestion and power noise reduction. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
3D module placement, power noise reduction, congestion, system-on-package |
| 1 | Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden |
Floorplan management: incremental placement for gate sizing and buffer insertion. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong |
Compact and stable modeling of partial inductance and reluctance matrices. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiqun Cao, Ruibing Lu, Cheng-Kok Koh |
Post-layout logic duplication for synthesis of domino circuits with complex gates. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Wai-Ching Douglas Lam, Cheng-Kok Koh |
Process variation robust clock tree routing. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruibing Lu, Aiqun Cao, Cheng-Kok Koh |
Improving the scalability of SAMBA bus architecture. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh |
A Performance and Power Co-optimization Approach for Modern Processors. |
CIT |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen |
Statistical based link insertion for robust clock network design. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Ateen Khatkhate, Chen Li 0004, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden |
Recursive bisection based mixed block placement. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
mixed block design, placement, floorplanning |
| 1 | Aiqun Cao, Cheng-Kok Koh |
Post-layout logic optimization of domino circuits. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
optimization, synthesis, layout, domino logic |
| 1 | Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh |
Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
SR algorithm, dominant eigenspace, stochastic balanced truncation, projection, model reduction, Riccati equation |
| 1 | Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruibing Lu, Cheng-Kok Koh |
A high performance bus communication architecture through bus splitting. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan |
Fast simulation of VLSI interconnects. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden |
Routability-driven placement and white space allocation. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
On-chip interconnect modeling by wire duplication. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao |
Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiran Chen, Kaushik Roy, Cheng-Kok Koh |
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
power supply noise, inductive noise |
| 1 | Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy |
An adaptive window-based susceptance extraction and its efficient implementation. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
interconnect, inductance, susceptance |
| 1 | Ruibing Lu, Cheng-Kok Koh |
Interconnect Planning with Local Area Constrained Retiming. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruibing Lu, Cheng-Kok Koh |
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruibing Lu, Cheng-Kok Koh |
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiqun Cao, Cheng-Kok Koh |
Non-Crossing OBDDs for Mapping to Regular Circuit Structures. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Wen Albert Tsao, Cheng-Kok Koh |
UST/DME: a clock tree router for general skew constraints. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
Useful Skew, feasible skew range, incremental skew scheduling, merging and embedding, merging region, clock tree |
| 1 | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao |
Power Supply Noise Suppression via Clock Skew Scheduling. (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
Skew Scheduling, Power noise, Clock |
| 1 | Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy |
Synthesis of Selectively Clocked Skewed Logic Circuits. (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh |
A factorization-based framework for passivity-preserving model reduction of RLC systems. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
passivity preserving, factorization, large scale systems, model reduction, RLC interconnect |
| 1 | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh |
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Krylov, large scale systems, model reduction, RLC interconnects, balanced truncation |
| 1 | Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao |
Flip-Flop and Repeater Insertion for Early Interconnect Planning. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy |
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
On-chip interconnect modeling by wire duplication. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Guoan Zhong, Cheng-Kok Koh |
Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Probir Sarkar, Cheng-Kok Koh |
Routability-driven repeater block planning for interconnect-centricfloorplanning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Cheng-Kok Koh, Patrick H. Madden |
Interconnect layout optimization under higher order RLC model forMCM designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan |
Interconnect sizing and spacing with consideration of couplingcapacitance. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes |
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy |
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. |
ISLPED |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh (eds.) |
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP BibTeX RDF |
|
| 1 | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
Decoupling capacitance allocation for power supply noise suppression. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
interconnect sizing, power and ground network design, convex optimization |
| 1 | Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes |
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Probir Sarkar, Cheng-Kok Koh |
Repeater block planning under simultaneous delay and transition time constraints. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Wang, Kaushik Roy, Cheng-Kok Koh |
Short-circuit power analysis of an inverter driving an RLC load. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes |
Power trends and performance characterization of 3-dimensional integration. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Kok Koh, Patrick H. Madden |
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh |
Routability-driven repeater block planning for interconnect-centric floorplanning. |
ISPD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
Frequency Domain Analysis of Switching Noise on Power Supply Network. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Chung-Wen Albert Tsao, Cheng-Kok Koh |
UST/DME: A Clock Tree Router for General Skew Constraints. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes |
Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar |
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. (PDF / PS) |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. (PDF / PS) |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
Bounded-skew clock and Steiner routing. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
(inter)connection, boundary merging and embedding, bounded-skew, interior merging and embedding, merging region, merging segment, pathlength delay, VLSI, low power, synchronization, Steiner tree, clock tree, Elmore delay, zero-skew |
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