|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 142 occurrences of 98 keywords
|
|
|
|
|
Results
Found 157 publication records. Showing 157 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li |
On test and repair of 3D random access memory.  |
ASP-DAC  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mincent Lee, Li-Ming Denq, Cheng-Wen Wu |
A Memory Built-In Self-Repair Scheme Based on Configurable Spares. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu |
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu |
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. |
ITC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chiou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang |
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
DfT Architecture for 3D-SICs with Multiple Towers. |
European Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
three-dimensional stacking, 3D-SIC, multi-tower, DfT, wrapper, design-for-test, TSV, through-silicon via |
| 1 | Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu |
A self-testing and calibration method for embedded successive approximation register ADC. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Wen Wu |
Special session: Hot topic design and test of 3D and emerging memories. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu |
Training-based forming process for RRAM yield improvement. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Yen Lo, Yu-Tsao Hsing, Li-Ming Denq, Cheng-Wen Wu |
SOC Test Architecture and Method for 3-D ICs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu |
Built-In Self-Repair Schemes for Flash Memories. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen-Hsing Wang, Chieh-Lin Chuang, Cheng-Wen Wu |
An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu, Chih-Tsun Huang |
Single- and Multi-core Configurable AES Architectures for Flexible Security. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao |
Diagnosis of MRAM Write Disturbance Fault. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mao-Yin Wang, Cheng-Wen Wu |
A Mesh-Structured Scalable IPsec Processor. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu |
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Tsao Hsing, Li-Ming Denq, Chao-Hsun Chen, Cheng-Wen Wu |
Economic Analysis of the HOY Wireless Test Methodology. |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
Performance Characterization of TSV in 3D IC via Sensitivity Analysis. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu |
A Test Integration Methodology for 3D Integrated Circuits. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu |
Fast identification of operating current for toggle MRAM by spiral search. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
reliability, testing, BIST, characterization, yield enhancement, MRAM |
| 1 | Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu |
An error tolerance scheme for 3D CMOS imagers. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
image sensor, error tolerance, 3D IC |
| 1 | Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li |
A low-cost and scalable test architecture for multi-core chips. |
European Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Cheng-Wen Wu |
Is 3D integration an opportunity or just a hype? |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai |
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Yi Chen, Cheng-Wen Wu |
An adaptive code rate EDAC scheme for random access memory. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu |
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. |
IEEE Design & Test of Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai |
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu |
Test Integration for SOC Supporting Very Low-Cost Testers. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu |
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ding-Yeong Wang, Yuan-Jen Lee, Ming-Jer Kao |
Write Disturbance Modeling and Testing for MRAM. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo |
A Systematic Approach to Memory Test Time Reduction. |
IEEE Design & Test of Computers |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu |
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Wen Wu |
SOC Testing Methodology and Practice |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Yen-Lin Peng, Cheng-Wen Wu, Jing-Jia Liou, Chih-Tsun Huang |
BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu |
STEAC: A Platform for Automatic SOC Test Integration. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu |
Economic Aspects of Memory Built-in Self-Repair. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair |
| 1 | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |
Raisin: Redundancy Analysis Algorithm Simulation. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
repair rate, BIRA, Raisin, yield, BISR, redundancy analysis, algorithm simulation |
| 1 | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao |
Diagnosis for MRAM write disturbance fault. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Tsao Hsing, Chun-Chieh Huang, Jen-Chieh Yeh, Cheng-Wen Wu |
SDRAM Delay Fault Modeling and Performance Testing. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu |
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin |
An Enhanced EDAC Methodology for Low Power PSRAM. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao |
Testing MRAM for Write Disturbance Fault. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang |
A network security processor design based on an integrated SOC design and test platform. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
HMAC-MD5, HMAC-SHA1, AES, RSA, AMBA, RNG |
| 1 | Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu |
A Built-In Self-Repair Scheme for NOR-Type Flash Memory. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Wen Wu |
Session Abstract. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu |
Fault-Pattern Oriented Defect Diagnosis for Flash Memory. |
MTDT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu |
A built-in self-repair design for RAMs with 2-D redundancy. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen |
Flash Memory Die Sort by a Sample Classification Method. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
die sort, test flow, wafer probe, flash memory, memory testing |
| 1 | Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu |
A configurable AES processor for enhanced security. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
Design and test of a scalable security processor. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu |
A BIST Scheme for FPGA Interconnect Delay Faults. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih, Cheng-Wen Wu, Chien-Hung Ho, Yen-Tai Lin |
Flash Memory Built-In Self-Diagnosis with Test Mode Control. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Wen Wu |
SOC Testing Methodology and Practice. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Lung Su, Yi-Ting Yeh, Cheng-Wen Wu |
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Pin Su, Cheng-Wen Wu |
A Graph-Based Approach to Power-Constrained SOC Test Scheduling. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
test integration, test scheduling, test access mechanism (TAM), SOC testing, test power, system-on-chip (SOC) |
| 1 | Bin-Hong Lin, Cheng-Wen Wu, Hwei-Tsu Ann Luh |
Efficient and Economical Test Equipment Setup Using Procorrelation. |
IEEE Design & Test of Computers |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu |
MRAM Defect Analysis and Fault Modeli. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng |
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu |
On Test and Diagnostics of Flash Memories. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang |
Fail Pattern Identification for Memory Built-In Self-Repair. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu |
An HMAC processor with integrated SHA-1 and MD5 algorithms. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu |
SRAM delay fault modeling and test algorithm development. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu |
Failure Factor Based Yield Enhancement for SRAM Designs. |
DFT |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu |
An Application-Independent Delay Testing Methodology for Island-Style FPGA. |
DFT |
2004 |
DBLP DOI BibTeX RDF |
segment delay fault, FPGA, delay testing, path delay fault |
| 1 | Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu |
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. |
MTDT |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu |
Built-in redundancy analysis for memory yield improvement. |
IEEE Transactions on Reliability |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Hua Hong, Cheng-Wen Wu |
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Hui Shieh, Cheng-Wen Wu |
Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition. |
J. Inf. Sci. Eng. |
2003 |
DBLP BibTeX RDF |
|
| 1 | Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu |
Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. |
J. Inf. Sci. Eng. |
2003 |
DBLP BibTeX RDF |
|
| 1 | Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu |
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
march test algorithm, memory diagnostics, BIST, memory testing, CAM |
| 1 | Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang |
Fault Pattern Oriented Defect Diagnosis for Memories. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
failure analysis (FA), fault pattern, memory diagnostics, memory testing, bitmap, semiconductor memory |
| 1 | Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow |
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair |
| 1 | Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu |
A Processor-Based Built-In Self-Repair Design for Embedded Memories. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu |
Defect Oriented Fault Analysis for SRAM. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
Test and Diagnosis of Word-Oriented Multiport Memories. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang |
Combinational circuit fault diagnosis using logic emulation. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li |
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. |
MTDT |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu |
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin |
A Hierarchical Test Methodology for Systems on Chip. |
IEEE Micro |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu |
Fault simulation and test algorithm generation for random accessmemories. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu |
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Cheng-Wen Wu |
Efficient FFT network testing and diagnosis schemes. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin |
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
memory BIST, memory diagnostics, memory testing, RAM, semiconductor memory |
| 1 | Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu |
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
Hamming syndrome, memory diagnostics, data compression, built-in self-test (BIST), system-on-chip, memory testing, Huffman code, March test |
| 1 | Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu |
Diagonal Test and Diagnostic Schemes for Flash Memorie. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
built-in self-diagnosis (BISD), memory diagnosis, built-in self-test (BIST), flash memory, memory testing, system-on-chip (SOC) |
| 1 | Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu |
Flash Memory Built-In Self-Test Using March-Like Algorithm. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin |
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu |
On-chip Analog Response Extraction with 1-Bit ? - Modulators. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin |
Test Scheduling of BISTed Memory Cores for SOC. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu |
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu |
Testing and Diagnosing Embedded Content Addressable Memories. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin |
A Hierarchical Test Scheme for System-On-Chip Designs. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
simulation, memory testing, embedded memory, redundancy analysis, memory repair |
| 1 | Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu |
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. |
MTDT |
2002 |
DBLP DOI BibTeX RDF |
simulation, memory testing, embedded memory, redundancy analysis, memory repair |
| 1 | Shih-Arn Hwang, Cheng-Wen Wu |
Unified VLSI systolic array design for LZ data compression. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu |
VLSI Design of RSA Cryptosystem Based on the Chinese Remainder Theorem. |
J. Inf. Sci. Eng. |
2001 |
DBLP BibTeX RDF |
|
| 1 | Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
March-based RAM diagnosis algorithms for stuck-at and coupling faults. |
ITC |
2001 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #100 of 157 (100 per page; Change: ) Pages: [ 1][ 2][ >>] |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")