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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 39 publication records. Showing 39 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee |
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree.  |
Integration  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee |
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee |
The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B. |
Journal of Circuits, Systems, and Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee |
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai |
Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems. |
J. Inf. Sci. Eng. |
2010 |
DBLP BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee |
Antenna Violation Avoidance/Fixing for X-clock routing. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee |
Double-via insertion enhanced X-architecture clock routing for reliability. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Trong-Yen Lee |
The Design of a Li-ion Battery Charger Based on Multimode LDO Technology. |
Journal of Circuits, Systems, and Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee |
A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters. |
Journal of Circuits, Systems, and Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee |
GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee |
Layer assignment considering manufacturability in X-architecture clock tree. |
CIT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao |
X-clock routing based on pattern matching. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee |
Zero-Skew Driven Buffered RLC Clock Tree Construction. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao |
Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems. |
IIH-MSP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao |
An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. |
IMECS |
2007 |
DBLP BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu |
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. |
J. Inf. Sci. Eng. |
2006 |
DBLP BibTeX RDF |
|
| 1 | Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai |
Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. |
ICICIC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee |
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao |
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao |
A single chip image sensor embedded smooth spatial filter with A/D conversion. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai |
Inductance extraction for general interconnect structures. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao |
Coupling aware RLC-based clock routings for crosstalk minimization. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang |
A new low-power turbo decoder using HDA-DHDD stopping iteration. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen |
A new CCII-based pipelined analog to digital converter. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee |
Zero-Skew Driven for RLC Clock Tree Construction in SoC. |
ICITA |
2005 |
DBLP DOI BibTeX RDF |
RLC delay model, Upward propagation, SoC, Clock tree, Zero skew |
| 1 | Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang |
RCGES: Retargetable Code Generation for Embedded Systems. |
ATVA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai |
Efficient routability check algorithms for segmented channel routing. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
field programmable gate arryas (FPGAs), segmented channel, routing |
| 1 | Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho |
An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai |
An Automatic Router for the Pin Grid Array Package. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai |
An Even Wiring Approach to the Ball Grid Array Package Routing. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen |
NEWS: a net-even-wiring system for the routing on a multilayer PGA package. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen |
Hmap: a fast mapper for EPGAs using extended GBDD hash tables. |
ACM Trans. Design Autom. Electr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng |
Performance driven bus buffer insertion. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin |
Performance driven multiple-source bus synthesis using buffer insertion. |
ASP-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Sao-Jie Chen |
A Linear Time Algorithm for Planar Moat Routing. |
J. Inf. Sci. Eng. |
1994 |
DBLP BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng |
An H-V alternating router. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng |
A knowledge-based program for compacting mask layout of integrated circuits. |
Computer-Aided Design |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng |
Generalized terminal connectivity problem for multilayer layout scheme. |
Computer-Aided Design |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng |
An H-V Tile-Expansion Router. |
J. Inf. Sci. Eng. |
1990 |
DBLP BibTeX RDF |
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