Search results for "Chia-Lin Yang"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng	A cycle-level SIMT-GPU simulation framework.	ISPASS	2012	DBLP DOI BibTeX RDF
1	Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang	Memory access aware power gating for MPSoCs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng	Power gating strategies on GPUs.	TACO	2011	DBLP DOI BibTeX RDF
1	Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen	TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang	Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang	A SAT-based routing algorithm for cross-referencing biochips.	SLIP	2011	DBLP DOI BibTeX RDF
1	Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang	Dynamic thermal management for networked embedded systems under harsh ambient temperature variation.	ISLPED	2010	DBLP DOI BibTeX RDF	electronic control unit, embedded system, thermal management, automotive electronics
1	Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang	Memory Latency Reduction via Thread Throttling.	MICRO	2010	DBLP DOI BibTeX RDF
1	Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang	PM-COSYN: PE and memory co-synthesis for MPSoCs.	DATE	2010	DBLP BibTeX RDF
1	Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang	Hierarchical memory scheduling for multimedia MPSoCs.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang, Yu-Jung Cheng	A Predictive Shutdown Technique for GPU Shader Processors.	Computer Architecture Letters	2009	DBLP DOI BibTeX RDF
1	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
1	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	T-trees: A tree-based representation for temporal and three-dimensional floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
1	Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang	An architectural co-synthesis algorithm for energy-aware Network-on-Chip design.	Journal of Systems Architecture - Embedded Systems Design	2009	DBLP DOI BibTeX RDF
1	Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang	A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sung-Wen Wang, Shu-Sian Yang, Hong-Ming Chen, Chia-Lin Yang, Ja-Ling Wu	A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Parallel algorithm, Video coding, SIMD, H.264/AVC, Deblocking filter
1	Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King	PPT: joint performance/power/thermal management of DRAM memory for multi-core systems.	ISLPED	2009	DBLP DOI BibTeX RDF	page allocation, scheduling, power, temperature, DRAM memory
1	Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu	Thermal modeling for 3D-ICs with integrated microchannel cooling.	ICCAD	2009	DBLP BibTeX RDF
1	Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang	Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng	Energy-Aware Flash Memory Management in Virtual Memory System.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang	A progressive-ILP based routing algorithm for cross-referencing biochips.	DAC	2008	DBLP DOI BibTeX RDF	progressive-ILP, routing, microfluidics, biochip
1	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Temporal floorplanning using the three-dimensional transitive closure subGraph.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	temporal floorplanning, Reconfigurable computing, partially dynamical reconfiguration
1	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.	JETC	2007	DBLP DOI BibTeX RDF	placement, Microfluidics, biochip
1	Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.	ISLPED	2007	DBLP DOI BibTeX RDF	post-placement optimization, scheduling, field-programmable gate array, leakage
1	Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang	Efficient obstacle-avoiding rectilinear steiner tree construction.	ISPD	2007	DBLP DOI BibTeX RDF	routing, spanning tree, physical design, Steiner tree
1	Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su	An architectural co-synthesis algorithm for energy-aware network-on-chip design.	SAC	2007	DBLP DOI BibTeX RDF
1	Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen	Cache leakage control mechanism for hard real-time systems.	CASES	2007	DBLP DOI BibTeX RDF	cache leakage control policy, hard real-time system
1	Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen	3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.	ICME	2007	DBLP DOI BibTeX RDF
1	Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King	Energy-efficient real-time task scheduling with task rejection.	DATE	2007	DBLP DOI BibTeX RDF	task rejection, energy-efficient scheduling, real-time task scheduling
1	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang	An energy-efficient virtual memory system with flash memory as the secondary storage.	ISLPED	2006	DBLP DOI BibTeX RDF	embedded storages, embedded systems, virtual memory, NAND flash memory, page replacement
1	Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King	Hierarchical value cache encoding for off-chip data bus.	ISLPED	2006	DBLP DOI BibTeX RDF	data bus encoding, hierarchical value cache, energy
1	Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen	Branch Behavior Characterization for Multimedia Applications.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Placement of digital microfluidic biochips using the t-tree formulation.	DAC	2006	DBLP DOI BibTeX RDF	placement, floorplanning, microfluidics, biochip
1	Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang	A Space-Efficient Caching Mechanism for Flash-Memory Address Translation.	ISORC	2006	DBLP DOI BibTeX RDF
1	Chia-Lin Yang, Hong-Wei Tseng, Chia-Chiang Ho, Ja-Ling Wu	Software-Controlled Cache Architecture for Energy Efficiency.	IEEE Trans. Circuits Syst. Video Techn.	2005	DBLP DOI BibTeX RDF
1	Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang	Joint exploration of architectural and physical design spaces with thermal consideration.	ISLPED	2005	DBLP DOI BibTeX RDF	architectural floorplanning, performance, thermal
1	Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung	Cache Leakage Management for Multi-programming Workloads.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen	Reconfigurable Platform for Content Science Research.	RTCSA	2005	DBLP DOI BibTeX RDF
1	Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee	Tolerating memory latency through push prefetching for pointer-intensive applications.	TACO	2004	DBLP DOI BibTeX RDF	linked data structures, pointer-chasing, Prefetch, memory hierarchy
1	Yen-Jen Chang, Feipei Lai, Chia-Lin Yang	Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Tse-Tsung Shih, Chia-Lin Yang, Yi-Shin Tung	Workload Characterization of the H.264/AVC Decoder.	PCM	2004	DBLP DOI BibTeX RDF
1	Chia-Lin Yang, Chien-Hao Lee	HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.	ISLPED	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, instruction cache
1	Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang	Profit-driven uniprocessor scheduling with energy and timing constraints.	SAC	2004	DBLP DOI BibTeX RDF	real-time process scheduling, embedded systems, power management, energy-aware scheduling
1	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen	Temporal floorplanning using 3D-subTCG.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, Chia-Lin Yang, Ai-Chun Pang, Tei-Wei Kuo	Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations.	ECRTS	2004	DBLP DOI BibTeX RDF	Real-Time Systems, Power Management, Multiprocessor Scheduling, Energy-Efficient Scheduling, Real-Time Task Scheduling
1	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.	DATE	2004	DBLP DOI BibTeX RDF
1	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Temporal floorplanning using the T-tree formulation.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang	Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	interrupt-emulation I/O, programmed I/O, embedded systems, energy-efficient, flash memory, storage systems
1	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	A power-aware SWDR cell for reducing cache write power.	ISLPED	2003	DBLP DOI BibTeX RDF	circuit-level, write power, low power, cache, SRAM
1	Wan-Chun Ma, Chia-Lin Yang	Using Intel Streaming SIMD Extensions for 3D Geometry Processing.	IEEE Pacific Rim Conference on Multimedia	2002	DBLP DOI BibTeX RDF
1	Chia-Lin Yang, Alvin R. Lebeck	A Programmable Memory Hierarchy for Prefetching Linked Data Structures.	ISHPC	2002	DBLP BibTeX RDF
1	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck	Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	geometry pipeline, paired-single instructions, 3D graphics, superscalar processors, SIMD instructions
1	Chia-Lin Yang, Alvin R. Lebeck	Push vs. pull: data movement for linked data structures.	ICS	2000	DBLP DOI BibTeX RDF
1	Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi	Annotated Memory References: A Mechanism for Informed Cache Management.	Euro-Par	1999	DBLP DOI BibTeX RDF
1	Chia-Lin Yang, Barton Sano, Alvin R. Lebeck	Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.	MICRO	1998	DBLP BibTeX RDF

Publications of "Chia-Lin Yang" ( http://dblp.L3S.de/Authors/Chia-Lin_Yang )