Search results for "Chien-In Henry Chen"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kiran George, Chien-In Henry Chen	A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement.	IEEE T. Instrumentation and Measurement	2011	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Delay optimization considering power saving in dynamic CMOS circuits.	ISQED	2011	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Yu-Heng George Lee, Chien-In Henry Chen	Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection.	IEEE T. Instrumentation and Measurement	2009	DBLP DOI BibTeX RDF
1	Kiran George, Chien-In Henry Chen	Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip.	IEEE T. Instrumentation and Measurement	2009	DBLP DOI BibTeX RDF
1	Yu-Heng George Lee, Chien-In Henry Chen	Dual Thresholding for Digital Wideband Receivers with Variable Truncation Scheme.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.	JCP	2008	DBLP DOI BibTeX RDF
1	Xinhui Zhang, Chien-In Henry Chen, Arvindkumar Chakravarthy	Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test.	IEEE T. Instrumentation and Measurement	2008	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
1	James Helton, Chien-In Henry Chen, David M. Lin, James B. Y. Tsui	FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver.	ISQED	2008	DBLP DOI BibTeX RDF	Instantaneous Frequency Measurement (IFM) receiver, wideband receiver, digital receiver
1	Yu-Heng George Lee, James Helton, Chien-In Henry Chen	Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Mingzhen Wang, Chien-In Henry Chen, Shailesh Radhakrishnan	Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS.	IEEE T. Instrumentation and Measurement	2007	DBLP DOI BibTeX RDF
1	Jason Wibbenmeyer, Chien-In Henry Chen	Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters.	IEEE T. Instrumentation and Measurement	2007	DBLP DOI BibTeX RDF
1	Kumar Yelamarthi, Chien-In Henry Chen	Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Kiran George, William McCormick, James B. Y. Tsui, Stephen L. Hary, Keith M. Graves	Design and performance evaluation of a 2.5-GSPS digital receiver.	IEEE T. Instrumentation and Measurement	2005	DBLP DOI BibTeX RDF
1	Shailesh Radhakrishnan, Mingzhen Wang, Chien-In Henry Chen	A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test.	IEEE T. Instrumentation and Measurement	2004	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].	ISCAS	2003	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen	Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults.	ISSS	2001	DBLP BibTeX RDF
1	Meghanad D. Wagh, Chien-In Henry Chen	High-level design synthesis with redundancy removal for high speed testable adders.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Anup Kumar	Comments on "Area-Time Optimal Adder Design".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	VLSI parallel adder, optimal 32-bit fast carry generator, fast carry generator, BiCMOS drivers, optimal adder design, adders, carry logic, critical path delay
1	Chien-In Henry Chen, Joel T. Yuen	Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design.	IEEE Trans. VLSI Syst.	1994	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Joel T. Yuen	Logic partitioning to pseudo-exhaustive test for BIST design.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen, Joel T. Yuen	Concurrent Test Scheduling in Built-In Self-Test Environment.	ICCD	1992	DBLP BibTeX RDF
1	Chien-In Henry Chen, Joel T. Yuen, Ji-Der Lee	Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment.	ICCD	1992	DBLP BibTeX RDF
1	Chien-In Henry Chen	Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit.	DAC	1991	DBLP DOI BibTeX RDF
1	Chien-In Henry Chen	BISTSYN - A Built-In Self-Test Synthesizer.	ICCAD	1991	DBLP BibTeX RDF
1	Chien-In Henry Chen	Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis.	ICCD	1991	DBLP BibTeX RDF

Publications of "Chien-In Henry Chen" ( http://dblp.L3S.de/Authors/Chien-In_Henry_Chen )