|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 2 occurrences of 2 keywords
|
|
|
|
|
Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin-Ngai Sze |
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.  |
ACM Great Lakes Symposium on VLSI  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael D. Moffitt, Chin-Ngai Sze |
Wire synthesizable global routing for timing closure. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shayak Banerjee, Kanak B. Agarwal, Chin-Ngai Sze, Sani R. Nassif, Michael Orshansky |
A methodology for propagating design tolerances to shape tolerances for use in manufacturing. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov |
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov |
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
static timing analysis, timing-driven placement |
| 1 | Tao Luo, David A. Papa, Zhuo Li, Chin-Ngai Sze, Charles J. Alpert, David Z. Pan |
Pyramids: an efficient computational geometry-based approach for timing-driven placement. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze |
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
Path-Based Buffer Insertion. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongqiang Lu, Chin-Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu |
Navigating Register Placement for Low Power Clock Network Design. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #9 of 9 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")