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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 34 occurrences of 31 keywords
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Results
Found 29 publication records. Showing 29 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
A low-power management technique for high-performance domino circuits.  |
ASP-DAC  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng |
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo |
Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo |
Dynamic voltage domain assignment technique for low power performance manageable cell based design. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng |
Built-in self at-speed delay binning and calibration mechanism in wireless test platform. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng |
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Hwa Cheng, Chin-Hsien Wang |
CKVdd: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng |
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
H.264, MPEG, Video decoder |
| 1 | Chen-I Chung, Shuo-Wen Chang, Ching-Hwa Cheng |
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing. |
ITC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li |
Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo |
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Chien Tsai, Ching-Hwa Cheng |
A full-synthesizable high-precision built-in delay time measurement circuit. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng |
A Multi-standard Video Decoder for High Definition Video Applications. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Hwa Cheng, Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung |
Design High-Performance and Low-Power Adder Cores with Full-Swing Nodes for Embedded Systems. |
IIH-MSP |
2009 |
DBLP DOI BibTeX RDF |
Embedded System, Low Power, Adder |
| 1 | Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang |
An All-Digital High-Precision Built-In Delay Time Measurement Circuit. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang 0003, Ching-Hwa Cheng |
Fixed-outline floorplanning using robust evolutionary search. |
Eng. Appl. of AI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hsiang-Hui Huang, Ching-Hwa Cheng |
Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang 0003, Ching-Hwa Cheng |
Noise-Aware Floorplanning for Fast Power Supply Network Design. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Hwa Cheng |
Design Scan Test Strategy for Single Phase Dynamic Circuits. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Hwa Cheng |
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits. (PDF / PS) |
DFT |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang |
Charge-sharing alleviation and detection for CMOS domino circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang |
Novel techniques for improving testability analysis. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
closed-form formulation, implication reasoning, TAIR, tree-structured circuit, logic testing, logic testing, controllability, controllability, built-in self test, automatic test pattern generation, BIST, observability, observability, stuck-at fault, shift registers, testability analysis, test patterns |
| 1 | Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang |
Charge sharing fault analysis and testing for CMOS domino logic circuits. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors |
| 1 | Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone |
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. (PDF / PS) |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang |
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone |
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. (PDF / PS) |
DFT |
1999 |
DBLP DOI BibTeX RDF |
charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit |
| 1 | Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng |
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors. |
IEEE Trans. Computers |
1997 |
DBLP DOI BibTeX RDF |
VLSI/WSI array processor, reconfiguration process, redundancy scheme, switch programming, yield simulation, performance analysis |
| 1 | Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen |
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
switching network fault diagnosis, reconfigurable VLSI/WSI array processors, switching network defects, killing error, testing circuit overhead, diagnosis time, mesh array, VLSI, parallel architectures, fault diagnosis, reconfigurable architectures, multiple faults, switching networks, wafer-scale integration, testing quality |
| 1 | Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou |
An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors. |
EDCC |
1994 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #29 of 29 (100 per page; Change: )
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