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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 34 publication records. Showing 34 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ching-Te Chiu, Yu-Hao Hsu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Yarsun Hsu |
An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking.  |
Signal Processing Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Rung Chen, Wei-Su Wong, Ching-Te Chiu |
A 0.64 mm 2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay, Cyuan-Jhe Wu |
Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. |
Signal Processing Systems |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Wei-Ming Ke, Chih-Rung Chen, Ching-Te Chiu |
BiTA/SWCE: Image Enhancement With Bilateral Tone Adjustment and Saliency Weighted Contrast Enhancement. |
IEEE Trans. Circuits Syst. Video Techn. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Wen-Chih Huang, Chih-Hsing Lin, Ching-Te Chiu |
Embedded transition inversion coding for low power serial link. |
SiPS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ruei-Jiun Wang, Ching-Te Chiu |
Saliency prediction using scene motion for JND based video compression. |
SiPS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ching-Te Chiu, Cyuan-Jhe Wu |
Texture classification based low order local binary pattern for face recognition. |
ICIP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Tsun-Hsien Wang, Ching-Te Chiu |
Low visual difference virtual high dynamic range image synthesizer from a single legacy image. |
ICIP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chih-Rung Chen, Ching-Te Chiu |
Curve-based and image-based JND contrast analysis for inverse tone mapping operators. |
ICIP |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu |
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, Chung-Kai Liu |
On the design and analysis of fault tolerant NoC architecture using spare routers. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sih-Kai Li, Jen-Shun Yang, Ching-Te Chiu, Po-Ting Yeh, Jenq-Neng Hwang |
Handover Delay Reduction and Buffer-Based Data Recovery Scheme for Inter Multicast Broadcast Service Zone. |
GLOBECOM |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fanta Chen, Min-Sheng Kao, Yu-Hao Hsu, Chih-Hsing Lin, Jen-Ming Wu, Ching-Te Chiu, Shuo-Hung Hsu |
A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu |
Switching Bilateral Filter With a Texture/Noise Detector for Universal Noise Removal. |
IEEE Transactions on Image Processing |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Hsing Lin, Jia Shiuan Tsai, Ching-Te Chiu |
Switching bilateral filter with a texture/noise detector for universal noise removal. |
ICASSP |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu |
A novel MUX-FF circuit for low power and high speed serial link interfaces. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Ming Ke, Ching-Te Chiu |
Hardware-efficient image enhancement with bilateral tone adjustment. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Chih-Hsing Lin, Yung-Chang Chang, Wen-Chih Huang, Wei-Chih Lai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Chun-Ming Huang, Chih-Chyau Yang, Shih-Lun Chen |
A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Yarsun Hsu |
A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu |
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18- $\mu$ m CMOS Technology. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Wei-Su Wong, Chih-Rung Chen, Ching-Te Chiu |
A 100MHz hardware-efficient boost cascaded face detection design. |
ICIP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Ming Ke, Tsun-Hsien Wang, Ching-Te Chiu |
Hardware-efficient virtual high dynamic range image reproduction. |
ICIP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay |
A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. |
SiPS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, Ren-Song Tsay |
Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. |
ICIP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu |
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Tsun-Hsien Wang, Wei-Su Wong, Fang-Chu Chen, Ching-Te Chiu |
Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video. |
ICIP |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Tsun-Hsien Wang, Wei-Ming Ke, Ding-Chuang Zwao, Fang-Chu Chen, Ching-Te Chiu |
Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Applications. |
ICIP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu |
A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron |
| 1 | Tsun-Hsien Wang, Ching-Te Chiu |
Low Power Design of High Performance Memory Access Architecture for HDTV Decoder. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu |
A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Hsing Lin, Ching-Te Chiu |
A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hou-Cheng Tzeng, Ching-Te Chiu |
A Flexible Cross Connect LCAS for Bandwidth Maximization in 2.5G EoS. |
NCA |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Te Chiu, Chun-Chieh Chang, Shih-Min Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, Kai-Ming Feng |
A 20 Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | K. J. Ray Liu, Ching-Te Chiu |
Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms. |
IEEE Transactions on Signal Processing |
1993 |
DBLP DOI BibTeX RDF |
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