Search results for "Ching-Te Chuang"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hao-I Yang, Wei Hwang, Ching-Te Chuang	Impacts of gate-oxide breakdown on power-gated SRAM.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Hao-I Yang, Wei Hwang, Ching-Te Chuang	Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang	SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, Ching-Te Chuang	Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Analysis of power-performance for ultra-thin-body GeOI logic circuits.	ISLPED	2011	DBLP BibTeX RDF
1	Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang	8T single-ended sub-threshold SRAM with cross-point data-aware write operation.	ISLPED	2011	DBLP BibTeX RDF
1	Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu	A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.	SoCC	2011	DBLP DOI BibTeX RDF
1	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy	Self-Repairing SRAM Using On-Chip Detection and Compensation.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang	Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang	Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability.	Microelectronics Reliability	2009	DBLP DOI BibTeX RDF
1	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
1	Ching-Te Chuang	Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Hao-I Yang, Ching-Te Chuang, Wei Hwang	Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang	A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang	Asymmetrical Write-assist for single-ended SRAM operation.	SoCC	2009	DBLP BibTeX RDF
1	Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das	Yield estimation of SRAM circuits using "Virtual SRAM Fab".	ICCAD	2009	DBLP BibTeX RDF
1	Koushik K. Das, Ching-Te Chuang, Richard B. Brown	Reducing parasitic BJT effects in partially depleted SOI digital logic circuits.	Microelectronics Journal	2008	DBLP DOI BibTeX RDF
1	Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka	Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang	Variability Analysis for sub-100nm PD/SOI Sense-Amplifier.	ISQED	2008	DBLP DOI BibTeX RDF	PD/SOI, dopant fluctuation, sense amplifier, Variation
1	Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.	ISQED	2008	DBLP DOI BibTeX RDF
1	Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.	VTS	2008	DBLP DOI BibTeX RDF	Design, yield, failure, SRAM, variation
1	Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang	Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang	Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.	ICCD	2008	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy	Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.	Microelectronics Journal	2007	DBLP DOI BibTeX RDF
1	Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong	Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI.	ISQED	2007	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	booster circuit, low power, yield, SRAM
1	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang	Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies.	ISLPED	2007	DBLP DOI BibTeX RDF	FD/SOI, low-power, stability, SRAM
1	Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang	A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy	Modeling and Analysis of Leakage Currents in Double-Gate Technologies.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang	High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy	Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
1	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.	ISLPED	2005	DBLP DOI BibTeX RDF	double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage
1	Rajiv V. Joshi, S. S. Kang, N. Zamdmar, A. Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez	Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang	Nanoscale CMOS circuit leakage power reduction by double-gate device.	ISLPED	2004	DBLP DOI BibTeX RDF	double-gate device, short-channel effect, leakage power
1	Rajiv V. Joshi, K. Kroell, Ching-Te Chuang	A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	R. Rodríguez, James H. Stathis, Barry P. Linder, Rajiv V. Joshi, Ching-Te Chuang	Influence and model of gate oxide breakdown on CMOS inverters.	Microelectronics Reliability	2003	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Ching-Te Chuang, S. K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi	PD/SOI SRAM performance in presence of gate-to-body tunneling current.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim	Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
1	Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang	Strained-si devices and circuits for low-power applications.	ISLPED	2003	DBLP DOI BibTeX RDF	band offset, strained-Si MOSFET, mobility, SOI, SiGe
1	Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown	New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.	ISLPED	2003	DBLP DOI BibTeX RDF	VLSI, high-performance, leakage-power, circuits, SOI
1	Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri	Design and CAD Challenges in sub-90nm CMOS Technologies.	ICCAD	2003	DBLP DOI BibTeX RDF
1	R. Rodríguez, James H. Stathis, Barry P. Linder, S. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, A. J. Bhavnagarwala, Salvatore Lombardo	Analysis of the effect of the gate oxide breakdown on SRAM stability.	Microelectronics Reliability	2002	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang	SOI for asynchronous dynamic circuits.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang	"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
1	Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang	A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Ruchir Puri, Ching-Te Chuang	SOI Digital Circuits: Design Issues.	VLSI Design	2000	DBLP DOI BibTeX RDF	Design, Digital Circuits, SOI
1	Ruchir Puri, Ching-Te Chuang	Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits.	ISLPED	1999	DBLP DOI BibTeX RDF
1	Ching-Te Chuang, Ruchir Puri	SOI Digital CMOS VLSI - a Design Perspective.	DAC	1999	DBLP DOI BibTeX RDF
1	Leon J. Sigal, James D. Warnock, Brian W. Curran, Yuen H. Chan, Peter J. Camporese, Mark D. Mayo, William V. Huott, Daniel R. Knebel, Ching-Te Chuang, James P. Eckhardt, Philip T. Wu	Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor.	IBM Journal of Research and Development	1997	DBLP DOI BibTeX RDF

Publications of "Ching-Te Chuang" ( http://dblp.L3S.de/Authors/Ching-Te_Chuang )