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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 23 occurrences of 21 keywords
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Results
Found 35 publication records. Showing 35 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chandan Karfa, Chitta Mandal, Dipankar Sarkar |
Verification of Register Transfer Level Low Power Transformations.  |
ISVLSI  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal |
Equivalence Checking of Array-Intensive Programs. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra |
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ariyam Das, Chittaranjan A. Mandal, Chris Reade, Manish Aasawat |
An improved greedy construction of minimum connected dominating sets in wireless networks. |
WCNC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandan Karfa, Dipankar Sarkar, Chitta Mandal |
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Rajiv Misra, Chittaranjan A. Mandal |
Minimum Connected Dominating Set Using a Collaborative Cover Heuristic for Ad Hoc Sensor Networks. |
IEEE Trans. Parallel Distrib. Syst. |
2010 |
DBLP DOI BibTeX RDF |
routing backbone, maximal independent set (MIS), Steiner tree, Connected dominating set (CDS) |
| 1 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra |
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal |
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Gopal Paul, Rohit Reddy, Chittaranjan A. Mandal, Bhargab B. Bhattacharya |
A BDD-Based Design of an Area-Power Efficient Asynchronous Adder. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Gopal Paul, Santosh Biswas, Chittaranjan A. Mandal, Bhargab B. Bhattacharya |
A BDD-based approach to design power-aware on-line detectors for digital circuits. |
SoCC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Rajiv Misra, Chittaranjan A. Mandal |
Efficient clusterhead rotation via domatic partition in self-organizing sensor networks. |
Wireless Communications and Mobile Computing |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Rajiv Misra, Chittaranjan A. Mandal |
Rotation of CDS via Connected Domatic Partition in Ad Hoc Sensor Networks. |
IEEE Trans. Mob. Comput. |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Rajiv Misra, Chittaranjan A. Mandal |
Location Updates of Mobile Node in Wireless Sensor Networks. |
MSN |
2009 |
DBLP DOI BibTeX RDF |
Sensor networks, Mobility, Location management, Connected dominating set |
| 1 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra |
Systematic Methodology for High-Level Performance Modeling of Analog Systems. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar |
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra |
A Fast Exploration Procedure for Analog High-Level Specification Translation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade |
A System for Automatic Evaluation of C Programs: Features and Interfaces. |
IJWLTT |
2007 |
DBLP BibTeX RDF |
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| 1 | Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade |
Hand-in-hand verification of high-level synthesis. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
FSMD model, formal verification, high-level synthesis, equivalence checking |
| 1 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade |
Register Sharing Verification During Data-Path Synthesis. |
ICCTA |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Vinay Vishwakarma, Chittaranjan A. Mandal, Shamik Sural |
Automatic Detection of Human Fall in Video. |
PReMI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajiv Misra, Chittaranjan A. Mandal |
ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks. |
COMSWARE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chittaranjan A. Mandal, Chris Reade |
Animating Algorithms over the Web. |
WEBIST |
2006 |
DBLP BibTeX RDF |
|
| 1 | Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade |
A System for Automatic Evaluation of Programs for Correctness and Performance. |
WEBIST (Selected Papers) |
2006 |
DBLP DOI BibTeX RDF |
Program Testing, XML Schema, Course Management System, Automatic Evaluation |
| 1 | Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade |
A System for Automatic Evaluation of Programs for Correctness and Performance. |
WEBIST |
2006 |
DBLP BibTeX RDF |
|
| 1 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade |
A Formal Verification Method of Scheduling in High-level Synthesis. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade |
Verification of Scheduling in High-level Synthesis. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra |
A formal approach for high level synthesis of linear analog systems. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
L2 sensitivity, analog high level synthesis, linear systems, architecture exploration, state space model |
| 1 | Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra |
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal |
A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Bipin Rajendran, Veerbhan Kheterpal, Abhishek Das, Jayanta Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti |
Timing analysis of tree-like RLC circuits. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose |
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Chittaranjan A. Mandal, R. M. Zimmer |
A Genetic Algorithm for the Synthesis of Structured Data Paths. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation |
| 1 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose |
A design space exploration scheme for data-path synthesis. |
IEEE Trans. VLSI Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose |
Design Space Exploration for Data Path Synthesis. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose |
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
Multi-port Memory, Genetic Algorithm, VLSI, Binding, Data Path Synthesis |
Displaying result #1 - #35 of 35 (100 per page; Change: )
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