| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jackey Z. Yan, Chris Chu |
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning.  |
ISPD  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak |
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaurav Ajwani, Chris Chu, Wai-Kei Mak |
FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanheng Zhang, Chris Chu |
RegularRoute: an efficient detailed router with regular routing patterns. |
ISPD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yue Xu, Chris Chu |
MGR: Multi-level global router. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jackey Z. Yan, Chris Chu |
DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yue Xu, Chris Chu |
A matching based decomposer for double patterning lithography. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
doubel patterning lithography, planar graph, matching algorithm |
| 1 | Gaurav Ajwani, Chris Chu, Wai-Kei Mak |
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
RSMT, spanning graph, routing, physical design |
| 1 | Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu |
ITOP: integrating timing optimization within placement. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
placement, timing optimization, physical synthesis |
| 1 | Jackey Z. Yan, Chris Chu, Wai-Kei Mak |
SafeChoice: a novel clustering algorithm for wirelength-driven placement. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
vlsi placement, physical design, hypergraph clustering |
| 1 | Yue Xu, Chris Chu |
An auction based pre-processing technique to determine detour in global routing. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu |
Handling routability in floorplan design with twin binary trees. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jackey Z. Yan, Natarajan Viswanathan, Chris Chu |
Handling complexities in modern large-scale mixed-size placement. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
incremental placement, mixed-size design, floorplanning |
| 1 | Yue Xu, Yanheng Zhang, Chris Chu |
FastRoute 4.0: global router with efficient via minimization. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang |
Pad assignment for die-stacking System-in-Package design. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yanheng Zhang, Chris Chu |
CROP: Fast and effective congestion refinement of placement. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yue Xu, Chris Chu |
GREMA: Graph reduction based efficient mask assignment for double patterning technology. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Chris C. N. Chu, Yiu-Chung Wong |
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris Chu |
Wire Sizing. |
Encyclopedia of Algorithms |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jackey Z. Yan, Chris Chu |
DeFer: deferred decision making enabled fixed-outline floorplanner. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
deferred decision making, floorplanning, fixed outline |
| 1 | Yanheng Zhang, Yue Xu, Chris Chu |
FastRoute3.0: a fast and high quality global router based on virtual capacity. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu |
Wire Retiming Problem With Net Topology Optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Pan, Chris C. N. Chu |
IPR: An Integrated Placement and Routing Algorithm. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu |
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Pan, Chris C. N. Chu |
FastRoute 2.0: A High-quality and Efficient Global Router. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
design solution quality, FastRoute 2.0, advanced IC technology, extremely fast global router, monotonic routing, multisource multisink maze routing, high-quality routing solutions |
| 1 | Natarajan Viswanathan, Min Pan, Chris C. N. Chu |
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
legalization technique, FastPlace 3.0, multilevel quadratic placement algorithm, placement congestion control, large-scale mixed-size designs, multilevel global placement framework, two-level clustering scheme, iterative local refinement, placement blockages, placement congestion constraints |
| 1 | Min Pan, Chris C. N. Chu, Priyadarshan Patra |
A Novel Performance-Driven Topology Design Algorithm. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia |
The coming of age of physical synthesis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu |
Optimal cell flipping in placement and floorplanning. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
flipping, placement, floorplanning, orientation, wirelength |
| 1 | Natarajan Viswanathan, Min Pan, Chris C. N. Chu |
FastPlace 2.0: an efficient analytical placer for mixed-mode designs. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan Lin, Hai Zhou, Chris C. N. Chu |
A revisit to floorplan optimization by Lagrangian relaxation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
floorplan, Lagrangian relaxation |
| 1 | Min Pan, Chris C. N. Chu |
FastRoute: a step to integrate global routing into placement. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu |
Post-placement voltage island generation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
tree, floorplanning, voltage island |
| 1 | Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu |
Analog placement with symmetry and other placement constraints. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
symmetry constraints, placement, analog circuits, sequence-pair |
| 1 | Sampath Dechu, Zion Cien Shen, Chris C. N. Chu |
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Natarajan Viswanathan, Chris C. N. Chu |
FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, Yiu-Chung Wong |
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
rectilinear steiner minimal tree algorithm, wirelength estimation, routing |
| 1 | Natarajan Viswanathan, Min Pan, Chris C. N. Chu |
FastPlace: an analytical placer for mixed-mode designs. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
mixed-mode placement, floorplanning, analytical placement |
| 1 | Min Pan, Chris C. N. Chu, J. Morris Chang |
Transition time bounded low-power clock tree construction. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Pan, Chris C. N. Chu, Hai Zhou |
Timing yield estimation using statistical static timing analysis. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Pan, Natarajan Viswanathan, Chris C. N. Chu |
An efficient and effective detailed placement algorithm. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li |
Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay |
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, Evangeline F. Y. Young |
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho |
Placement constraints in floorplan design. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Natarajan Viswanathan, Chris C. N. Chu |
FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
net models, analytical placement, standard cell placement |
| 1 | Debjit Sinha, Hai Zhou, Chris C. N. Chu |
Optimal gate sizing for coupling-noise reduction. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
coupling-noise, gate-sizing, lattice theory, fixpoint |
| 1 | Sampath Dechu, Zion Cien Shen, Chris C. N. Chu |
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Zion Cien Shen, Chris C. N. Chu |
Accurate and efficient flow based congestion estimation in floorplanning. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu |
Fitted Elmore delay: a simple and accurate interconnect delay model. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris Chu |
FLUTE: fast lookup table based wirelength estimation technique. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Berleant, Mei-Peng Cheong, Chris C. N. Chu, Yong Guan, Ahmed E. Kamal, Gerald Shedblé, Scott Ferson, James F. Peters |
Dependable Handling of Uncertainty. |
Reliable Computing |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen |
Twin binary sequences: a nonredundant representation for general nonslicing floorplan. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Zion Cien Shen, Chris C. N. Chu |
Bounds on the number of slicing, mosaic, and general floorplans. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu |
A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu |
Retiming with Interconnect and Gate Delay. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz |
Optimizing SOC Test Resources using Dual Sequences. |
VLSI-SOC |
2003 |
DBLP BibTeX RDF |
|
| 1 | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay |
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen |
Twin binary sequences: a non-redundant representation for general non-slicing floorplan. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho |
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
placement constraint, physical design, floorplanning |
| 1 | Chris C. N. Chu, Evangeline F. Y. Young |
Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu |
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, D. F. Wong |
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing |
| 1 | Yu-Yen Mo, Chris C. N. Chu |
Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong |
Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, D. F. Wong |
VLSI Circuit Performance Optimization by Geometric Programming. |
Annals OR |
2001 |
DBLP DOI BibTeX RDF |
unary geometric programming, circuit performance optimization, VLSI design, Lagrangian relaxation, gate sizing, transistor sizing, wire sizing |
| 1 | Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong |
Floorplan area minimization using Lagrangian relaxation. |
ISPD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Yen Mo, Chris C. N. Chu |
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization. |
ISPD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong |
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, Martin D. F. Wong |
An efficient and optimal algorithm for simultaneous buffer and wire sizing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, Martin D. F. Wong |
Greedy wire-sizing is linear time. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, Martin D. F. Wong |
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Fung Yu Young, Chris C. N. Chu, D. F. Wong |
Generation of Universal Series-Parallel Boolean Functions. |
J. ACM |
1999 |
DBLP DOI BibTeX RDF |
series-parallel Boolean functions, universal functions, FPGA, technology mapping |
| 1 | Chris C. N. Chu, Martin D. F. Wong |
A matrix synthesis approach to thermal placement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, D. F. Wong |
Greedy wire-sizing is linear time. |
ISPD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, D. F. Wong |
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing |
| 1 | Chung-Ping Chen, Chris C. N. Chu, D. F. Wong |
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, D. F. Wong |
Closed form solution to simultaneous buffer insertion/sizing and wire sizing. |
ISPD |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, D. F. Wong |
A matrix synthesis approach to thermal placement. |
ISPD |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris C. N. Chu, D. F. Wong |
A new approach to simultaneous buffer insertion and wire sizing. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing |
| 1 | Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wei-Kei Mak |
Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. |
J. Parallel Distrib. Comput. |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wai-Kei Mak |
Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. |
SPDP |
1993 |
DBLP BibTeX RDF |
|
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