Search results for "Christian Landrault"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Is triple modular redundancy suitable for yield improvement?	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF
1	Christian Landrault	Something I Always Wanted to Know About Test, But Was Afraid to Ask.	European Test Symposium	2009	DBLP DOI BibTeX RDF
1	Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	DfT, Scan, Test data compression, Low power testing
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	SoC Yield Improvement: Redundant Architectures to the Rescue?	ITC	2008	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Improving Diagnosis Resolution without Physical Information.	DELTA	2008	DBLP DOI BibTeX RDF	Logic Diagnosis, Fault Modeling, Path Tracing
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Using TMR Architectures for Yield Improvement.	DFT	2008	DBLP DOI BibTeX RDF
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Yield Improvement, Fault-Tolerance to the Rescue?.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Christian Landrault, Erik Jan Marinissen	Editorial.	IET Computers & Digital Techniques	2007	DBLP BibTeX RDF
1	Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga	A concurrent approach for testing address decoder faults in eFlash memories.	ITC	2007	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	DERRIC: A Tool for Unified Logic Diagnosis.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.	VTS	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.	VTS	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Slow write driver faults in 65nm SRAM technology: analysis and March test solution.	DATE	2007	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Mixed Approach for Unified Logic Diagnosis.	DDECS	2007	DBLP BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
1	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	An Overview of Failure Mechanisms in Embedded Flash Memories.	VTS	2006	DBLP DOI BibTeX RDF
1	Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Power-Driven Routing-Constrained Scan Chain Design.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	scan chain design, DfT, low power testing, scan testing
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DELTA	2004	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DATE	2004	DBLP DOI BibTeX RDF
1	Christian Landrault	Guest Editorial.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF
1	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	A Unified DFT Approach for BIST and External Test.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	BIST, DFT, test point insertion, partial reset
1	Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	pseudo-random testing, deterministic BIST, logic BIST
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.	ITC	2003	DBLP DOI BibTeX RDF
1	Christian Landrault	Guest Editorial.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF
1	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Hardware Generation of Random Single Input Change Test Sequences.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	single input change, generation, hardware, random testing, test sequence
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich	High Defect Coverage with Low-Power Test Sequences in a BIST Environment.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Power Driven Chaining of Flip-Flops in Scan Architectures.	ITC	2002	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Test Power: a Big Issue in Large SOC Designs.	DELTA	2002	DBLP DOI BibTeX RDF	DfT, BIST, Scan, Low Power Testing, Test Power
1	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	On Using Efficient Test Sequences for BIST.	VTS	2002	DBLP DOI BibTeX RDF
1	Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	non-robust test, BIST, random testing, delay testing, robust test
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	David Bernard, Christian Landrault, Pascal Nouet	Interconnect Capacitance Modelling in a VDSM CMOS Technology.	VLSI-SOC	2001	DBLP BibTeX RDF
1	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Random Adjacent Sequences: An Efficient Solution for Logic BIST.	VLSI-SOC	2001	DBLP BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.	VTS	2001	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan-Based BIST.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Paulo J. Teixeira, Marcelino B. Santos	Low Power BIST by Filtering Non-Detecting Vectors.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	low power BIST, low energy consumption, LFSR, gated clock
1	Christian Landrault	Guest Editorial.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch	Low power BIST design by hypergraph partitioning: methodology and architectures.	ITC	2000	DBLP DOI BibTeX RDF
1	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
1	Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault	Hidden Markov and Independence Models with Patterns for Sequential BIST.	VTS	2000	DBLP DOI BibTeX RDF	Machine Learning, HMM, Sequential Circuit, BIST
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.	IOLTW	2000	DBLP DOI BibTeX RDF	BIST, Random Testing, Delay Testing, Bridging Faults
1	Christian Landrault	Guest Editorial.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	BIST, delay faults, scan design
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	BIST Design, Test, Low-power Design, Energy Consumption
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	test vector ordering, test, low power, switching activity
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Inhibiting Technique for Low Energy BIST Design.	VTS	1999	DBLP DOI BibTeX RDF
1	A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet	Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts.	DATE	1999	DBLP DOI BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A BIST Structure to Test Delay Faults in a Scan Environment.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac	A non-iterative gate resizing algorithm for high reduction in power consumption.	Integration	1997	DBLP DOI BibTeX RDF
1	Christophe Fagot, Patrick Girard, Christian Landrault	On Using Machine Learning for Logic BIST.	ITC	1997	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac	A gate resizing technique for high reduction in power consumption.	ISLPED	1997	DBLP DOI BibTeX RDF
1	Marc Perbost, Ludovic Le Lan, Christian Landrault	Automatic Testability Analysis of Boards and MCMs at Chip Level.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	DFT, testability analysis, MCM
1	J. Abraham, P. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse	Hardware Test: Can We Learn from Software Testing? (PDF / PS)	VTS	1997	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms.	ITC	1996	DBLP DOI BibTeX RDF
1	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch	An advanced diagnostic method for delay faults in combinational faulty circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	simulation, diagnosis, delay fault, critical path tracing
1	Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre	Is High-Level Test Synthesis Just Design for Test?	ITC	1995	DBLP DOI BibTeX RDF
1	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault	Test configurations to enhance the testability of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	shift operation, scan register, test operation, modified flip-flops, ISCAS89 benchmarks, multiconfiguration, triconfiguration, dynamic generation, logic testing, controllability, design for testability, design for testability, sequential circuits, sequential circuits, observability, observability, DFT, fault coverage, flip-flops, minimisation, scan designs, test application time, test vector
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	Diagnostic of path and gate delay faults in non-scan sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, self-masking identification, fault diagnosis, fault diagnosis, logic testing, delays, integrated circuit testing, sequential circuits, automatic testing, integrated logic circuits, path delay faults, synchronous sequential circuits, path tracing, gate delay faults
1	D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis.	EDAC-ETC-EUROASIC	1994	DBLP BibTeX RDF
1	D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation.	ITC	1993	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Delay-Fault Diagnosis by Critical-Path Tracing.	IEEE Design & Test of Computers	1992	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch	A Novel Approach to Delay-Fault Diagnosis.	DAC	1992	DBLP BibTeX RDF
1	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch	Fault modeling and fault equivalence in CMOS technology.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	test generation, Fault modeling, fault collapsing, fault equivalence
1	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch	Fault modelling and fault equivalence in CMOS technology.	EURO-DAC	1990	DBLP DOI BibTeX RDF	Fault modelling, Test pattern generation, Fault collapsing
1	Yves Crouzet, Christian Landrault	Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF
1	Alain Costes, Christian Landrault, Jean-Claude Laprie	Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	hardware and software modeling, hardware and software redundancy, Markov and semi-Markov models, reliability, Availability
1	Christian Landrault, Jean-Claude Laprie	SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems.	Jerusalem Conference on Information Technology	1978	DBLP BibTeX RDF

Publications of "Christian Landrault" ( http://dblp.L3S.de/Authors/Christian_Landrault )