Search results for "Chuan-Yu Wang"

Found 5 publication records. Showing 5 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Chuan-Yu Wang, Kaushik Roy	Maximum power estimation for CMOS circuits using deterministic and statistical approaches.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Chuan-Yu Wang, Kaushik Roy	COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	CMOS Digital Circuits, Reliability, Power Estimation
1	Chuan-Yu Wang, Kaushik Roy	Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions.	ICCD	1997	DBLP BibTeX RDF
1	Chuan-Yu Wang, Kaushik Roy	Maximum power estimation for CMOS circuits using deterministic and statistic approaches.	VLSI Design	1996	DBLP DOI BibTeX RDF	maximum power estimation, deterministic approach, instantaneous power consumption, ATG technique, Monte Carlo based technique, computational complexity, VLSI, lower bound, statistical analysis, automatic testing, circuit analysis computing, Monte Carlo methods, automatic test generation, VLSI circuits, CMOS circuits, CMOS digital integrated circuits, statistic approach
1	Chuan-Yu Wang, Kaushik Roy	Control unit synthesis targeting low-power processors. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming

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Publications of "Chuan-Yu Wang" ( http://dblp.L3S.de/Authors/Chuan-Yu_Wang )