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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 7 keywords
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Results
Found 19 publication records. Showing 19 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits.  |
ASP-DAC  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng |
Accurate TSV Number Minimization in High-Level Synthesis. |
J. Inf. Sci. Eng. |
2011 |
DBLP BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. |
J. Inf. Sci. Eng. |
2010 |
DBLP BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Minimum-Period Register Binding. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng |
Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. |
J. Inf. Sci. Eng. |
2009 |
DBLP BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan |
Synthesis of Anti-Aging Gated Clock Designs. |
J. Inf. Sci. Eng. |
2009 |
DBLP BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Timing driven power gating in high-level synthesis. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang |
Surge Current Minimization in High-level Synthesis. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Power-Management Scheduling for Peak Power Minimization. |
J. Inf. Sci. Eng. |
2008 |
DBLP BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh |
Clock Period Minimization with Minimum Delay Insertion. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng |
Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. |
EUC Workshops |
2007 |
DBLP DOI BibTeX RDF |
Cycle-by-cycle Power Differential, Low Power, High-Level Synthesis, Integer Linear Programming, Operation Scheduling, Data-Path Synthesis |
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
An ILP Approach to the Slack Driven Scheduling Problem. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu |
Register binding for clock period minimization. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
high-level synthesis, clock skew, timing optimization |
| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang |
Peak Power Minimization through Power Management Scheduling. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Operation Scheduling for False Loop Free Circuits. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang |
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. |
JCIS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng |
Three-dimension scheduling under multi-cycle interconnect communications. |
IEICE Electronic Express |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
A formal approach to the slack driven scheduling problem in high-level synthesis. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
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