|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 3 occurrences of 3 keywords
|
|
|
|
|
Results
Found 10 publication records. Showing 10 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee |
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree.  |
Integration  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee |
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee |
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee |
Antenna Violation Avoidance/Fixing for X-clock routing. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee |
Double-via insertion enhanced X-architecture clock routing for reliability. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee |
Layer assignment considering manufacturability in X-architecture clock tree. |
CIT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao |
X-clock routing based on pattern matching. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee |
Zero-Skew Driven Buffered RLC Clock Tree Construction. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee |
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee |
Zero-Skew Driven for RLC Clock Tree Construction in SoC. |
ICITA |
2005 |
DBLP DOI BibTeX RDF |
RLC delay model, Upward propagation, SoC, Clock tree, Zero skew |
Displaying result #1 - #10 of 10 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")