Search results for "Chung-Kuan Cheng"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong	A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong	Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints".	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng	Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph.	ISPD	2012	DBLP DOI BibTeX RDF
1	Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham	Character design and stamp algorithms for Character Projection Electron-Beam Lithography.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham	Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng	On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng	Prediction and Comparison of High-Performance On-Chip Global Interconnection.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong	More realistic power grid verification based on hierarchical current and power constraints.	ISPD	2011	DBLP DOI BibTeX RDF
1	Chung-Kuan Cheng	Placement and beyond in honor of Ernest S. Kuh.	ISPD	2011	DBLP DOI BibTeX RDF
1	Zheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong	A block-diagonal structured model reduction scheme for power grid networks.	DATE	2011	DBLP BibTeX RDF
1	Shih-Hung Weng, Peng Du, Chung-Kuan Cheng	A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng	Efficient Power Network Analysis with Modeling of Inductive Effects.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng	Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Peng Du, Xiang Hu, Shih-Hung Weng, Amirali Shayan Arani, Xiaoming Chen, A. Ege Engin, Chung-Kuan Cheng	Worst-case noise prediction with non-zero current transition times for early power distribution system verification.	ISQED	2010	DBLP DOI BibTeX RDF
1	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	Bus via reduction based on floorplan revising.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	floorplan revising, via reduction, bus routing
1	Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng	Physical synthesis of bus matrix for high bandwidth low power on-chip communications.	ISPD	2010	DBLP DOI BibTeX RDF	wire efficiency, bandwidth, power efficiency
1	Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng	Performance prediction of throughput-centric pipelined global interconnects with voltage scaling.	SLIP	2010	DBLP DOI BibTeX RDF
1	Chung-Kuan Cheng, Amirali Shayan Arani, Andrew B. Kahng, Kambiz Samadi	Worst-case performance prediction under supply voltage and temperature variation.	SLIP	2010	DBLP DOI BibTeX RDF
1	Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng	An adaptive parallel flow for power distribution network simulation using discrete Fourier transform.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng	On-chip power network optimization with decoupling capacitors and controlled-ESRs.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng	Enabling power distribution network analysis flows for 3D ICs.	3DIC	2010	DBLP DOI BibTeX RDF
1	Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng	Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Wenjian Yu, Rui Shi, Chung-Kuan Cheng	Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Yi Zhu, Yuanfang Hu, Michael Bedford Taylor, Chung-Kuan Cheng	Energy and switch area optimizations for FPGA global routing architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, low power, global routing
1	Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Efficient Power Network Analysis Considering Multidomain Clock Gating.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Yi Zhu, Thomas Weng, Chung-Kuan Cheng	Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards.	IEEE Trans. Education	2009	DBLP DOI BibTeX RDF
1	Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng	Efficient power network analysis with complete inductive modeling.	ISQED	2009	DBLP DOI BibTeX RDF
1	Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng	Design methodology of high performance on-chip global interconnect using terminated transmission-line.	ISQED	2009	DBLP DOI BibTeX RDF
1	Amirali Shayan Arani, Xiang Hu, He Peng, Wenjian Yu, Wanping Zhang, Chung-Kuan Cheng, Mikhail Popovich, Xiaoming Chen, Lew Chua-Eoan, Xiaohua Kong	Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network.	ISQED	2009	DBLP DOI BibTeX RDF
1	Renshen Wang, Chung-Kuan Cheng	On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	3-D integrated circuits, cuboidal dual, computational complexity
1	Renshen Wang, Chung-Kuan Cheng	Octilinear redistributive routing in bump arrays.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	8-geometry, routing grid, network flow, interchangeability
1	Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng	Prediction of high-performance on-chip global interconnection.	SLIP	2009	DBLP DOI BibTeX RDF	on-chip global interconnection, performance prediction, transmission line
1	Xiang Hu, Wenbo Zhao, Peng Du, Yulei Zhang, Amirali Shayan Arani, Christopher Pan, A. Ege Engin, Chung-Kuan Cheng	On the bound of time-domain power supply noise based on frequency-domain target impedance.	SLIP	2009	DBLP DOI BibTeX RDF	target impedance, voltage noise, power distribution network
1	Chung-Kuan Cheng, Sherief Reda (eds.)	The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings	SLIP	2009	DBLP BibTeX RDF
1	Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng	Predicting the worst-case voltage violation in a 3D power network.	SLIP	2009	DBLP DOI BibTeX RDF	worst case violation prediction, integer linear programming, leakage, clock gating, power networks
1	Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng	Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.	DAC	2009	DBLP DOI BibTeX RDF	Steiner graph, gated bus, power efficiency
1	He Peng, Chung-Kuan Cheng	Parallel transistor level circuit simulation using domain decomposition methods.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng	High performance on-chip differential signaling using passive compensation for global communication.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng	Noise minimization during power-up stage for a multi-domain power network.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	He Peng, Chung-Kuan Cheng	Parallel transistor level full-chip circuit simulation.	DATE	2009	DBLP BibTeX RDF
1	Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen	Reliability aware through silicon via planning for 3D stacked ICs.	DATE	2009	DBLP BibTeX RDF
1	Chung-Kuan Cheng	Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders.	IEEE Symposium on Computer Arithmetic	2009	DBLP DOI BibTeX RDF
1	Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng	Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.	ICCD	2009	DBLP DOI BibTeX RDF
1	Amirali Shayan Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Ege Engin, Xiaoming Chen, Mikhail Popovich	3D stacked power distribution considering substrate coupling.	ICCD	2009	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng	Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng	Clock Skew Analysis via Vector Fitting in Frequency Domain.	ISQED	2008	DBLP DOI BibTeX RDF	vector fitting, clock skew, frequency domain
1	Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng	3-D floorplanning using labeled tree and dual sequences.	ISPD	2008	DBLP DOI BibTeX RDF	3-D packing, sequence, labeled tree
1	Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng	Low power passive equalizer optimization using tritonic step response.	DAC	2008	DBLP DOI BibTeX RDF	low power, equalizer, transmission line
1	Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto	High performance current-mode differential logic.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng	Timing-power optimization for mixed-radix Ling adders by integer linear programming.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng	Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.	DATE	2008	DBLP DOI BibTeX RDF
1	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng	A novel fixed-outline floorplanner with zero deadspace for hierarchical design.	ICCAD	2008	DBLP DOI BibTeX RDF	floorplanner, soft modules, zero deadspace, fixed-outline
1	Yi Zhu, Michael Bedford Taylor, Scott B. Baden, Chung-Kuan Cheng	Advancing supercomputer performance through interconnection topology synthesis.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh	Efficient and accurate eye diagram prediction for high speed signaling.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng	On-chip high performance signaling using passive compensation.	ICCD	2008	DBLP DOI BibTeX RDF
1	Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng	Low Power Passive Equalizer Design for Computer Memory Links.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	passive equalization, low power
1	Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh	Two-Stage Newton-Raphson Method for Transistor-Level Simulation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng	Efficient Timing Analysis With Known False Paths Using Biclique Covering.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng	Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.	ISQED	2007	DBLP DOI BibTeX RDF
1	Haikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris	An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization.	ASP-DAC	2007	DBLP DOI BibTeX RDF	64 bit, interconnect-centric approach, fanout splitting, cell order optimization, logarithmic cyclic shifter design, demultiplexers, shifting path, nonshifting paths, accumulated wire load, switching probabilities, integer linear programming
1	Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.	ASP-DAC	2007	DBLP DOI BibTeX RDF	optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder
1	Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen	Approaching Speed-of-light Distortionless Communication for On-chip Interconnect.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.10 micron, speed-of-light distortionless communication, surfliner on-chip distortionless transmission line scheme, shunt resistors, shunt conductance, single-ended microstrip line, 10 Gbit/s, on-chip interconnect
1	Amirali Shayan Arani, Yi Zhu, Yi-Ning Cheng, Chung-Kuan Cheng, Shien-Fong Lin, Peng-Sheng Chen	Exploring Cardioneural Signals from Noninvasive ECG Measurement.	BIBE	2007	DBLP DOI BibTeX RDF
1	He Peng, Chung-Kuan Cheng	Fast Transient Simulation of Lossy Transmission Lines.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Wanping Zhang, Chung-Kuan Cheng	Incremental Power Impedance Optimization Using Vector Fitting Modeling.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Yuanfang Hu, Yi Zhu, Michael Bedford Taylor, Chung-Kuan Cheng	FPGA global routing architecture optimization using a multicommodity flow approach.	ICCD	2007	DBLP DOI BibTeX RDF
1	Chun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng	Passive compensation for high performance inter-chip communication.	ICCD	2007	DBLP DOI BibTeX RDF
1	Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Fast power network analysis with multiple clock domains.	ICCD	2007	DBLP DOI BibTeX RDF
1	Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham	On the construction of zero-deficiency parallel prefix circuits with minimum depth.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Zero-deficiency, depth-size trade-off, parallel prefix circuits
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu	General Floorplans with L/T-Shaped Blocks Using Corner Block List.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	corner block list, L/T-shaped blocks, floorplanning
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Integrating dynamic thermal via planning with 3D floorplanning algorithm.	ISPD	2006	DBLP DOI BibTeX RDF	3D floorplanning, thermal optimization, thermal via
1	Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng	Communication latency aware low power NoC synthesis.	DAC	2006	DBLP DOI BibTeX RDF	network-on-chip, topology, power, latency
1	Rui Shi, Chung-Kuan Cheng	Efficient escape routing for hexagonal array of high density I/Os.	DAC	2006	DBLP DOI BibTeX RDF	BGA, flip chip, hexagonal array, escape routing
1	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton	Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.	ASP-DAC	2006	DBLP DOI BibTeX RDF	biclique covering, false subgraphs, multi-cycle subgraphs, static timing analysis, time shifting
1	Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh	An unconditional stable general operator splitting method for transistor level transient analysis.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Yi Zhu, Tong Lee Chen, Wanping Zhang, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng	Noninvasive Study of the Human Heart using Independent Component Analysis.	BIBE	2006	DBLP BibTeX RDF
1	Jianhua Liu, Michael Chang, Chung-Kuan Cheng	An iterative division algorithm for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, low power, high performance, division
1	Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng	Timing model reduction for hierarchical timing analysis.	ICCAD	2006	DBLP DOI BibTeX RDF	biclique-star replacement, hierarchical timing analysis
1	Renshen Wang, Rui Shi, Chung-Kuan Cheng	Layer minimization of escape routing in area array packaging.	ICCAD	2006	DBLP DOI BibTeX RDF	bottleneck analysis, central triangular pattern, escape routing
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu	Buffer planning as an Integral part of floorplanning with consideration of routing congestion.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao	The Y architecture for on-chip interconnect: analysis and methodology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.	ISQED	2005	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng	Buffer Planning Algorithm Based on Partial Clustered Floorplanning.	ISQED	2005	DBLP DOI BibTeX RDF
1	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris	Unified quadratic programming approach for mixed mode placement.	ISPD	2005	DBLP DOI BibTeX RDF	mixed mode placement, discrete cosine transformation, quadratic programming
1	Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh	Efficient transient simulation for transistor-level analysis.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham	Constructing zero-deficiency parallel prefix adder of minimum depth.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Hongyu Chen, Chung-Kuan Cheng	A multi-level transmission line network approach for multi-giga hertz clock distribution.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng	Integrated algorithmic logical and physical design of integer multiplier.	ASP-DAC	2005	DBLP DOI BibTeX RDF	booth, interconnect, partial product, TDM
1	Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen	Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	VLSI block placement with alignment constraints based on corner block list.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng	Performance constrained floorplanning based on partial clustering [IC layout].	ISCAS	2005	DBLP DOI BibTeX RDF
1	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris	Improving the efficiency of static timing analysis with false paths.	ICCAD	2005	DBLP BibTeX RDF
1	Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris	Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications.	ICCD	2005	DBLP DOI BibTeX RDF
1	Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng	Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz.	ICCD	2005	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Stairway compaction using corner block list and its applications with rectilinear blocks.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	corner block list, rectilinear blocks, Floorplanning
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu	A buffer planning algorithm for chip-level floorplanning.	Science in China Series F: Information Sciences	2004	DBLP DOI BibTeX RDF
1	Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Corner block list representation and its application with boundary constraints.	Science in China Series F: Information Sciences	2004	DBLP DOI BibTeX RDF
1	Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu	UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai	Area minimization of power distribution network using efficient nonlinear programming techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF

Publications of "Chung-Kuan Cheng" ( http://dblp.L3S.de/Authors/Chung-Kuan_Cheng )