Search results for "Chunhong Chen"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu	Low Power Chien Search for BCH Decoder Using RT-Level Power Management.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Shu-Yi Wong, Chunhong Chen	Power efficient multi-stage CMOS rectifier design for UHF RFID tags.	Integration	2011	DBLP DOI BibTeX RDF
1	Chunni Dai, Meng Yao, Zhujie Xie, Chunhong Chen, Jingao Liu	Parameter optimization for growth model of greenhouse crop using genetic algorithms.	Appl. Soft Comput.	2009	DBLP DOI BibTeX RDF
1	Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu	Power-management-based Chien search for low power BCH decoder.	ISLPED	2009	DBLP DOI BibTeX RDF	BCH decoder, Chien search, low power, power management
1	Venketeshwaran Puthucode, Chunhong Chen	An experimental study on multi-island structures for single-electron tunneling based threshold logic.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Mohammed Berhea, Chunhong Chen, Q. M. Jonathan Wu	Protocol-level performance analysis for anti-collision protocols in RFID systems.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu	Quasi-Static Energy Recovery Logic with Single Power-Clock Supply.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Jialin Mi, Chunhong Chen	Finite State Machine Implementation with Single-Electron Tunneling Technology.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Jialin Mi, Chunhong Chen	Power-Oriented Delay Budgeting for Combinational Circuits.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Yanjie Mao, Chunhong Chen	Performance Evaluation and Optimization of Full Adders with Single-Electron Technology.	CCECE	2006	DBLP DOI BibTeX RDF
1	Jialin Mi, Chunhong Chen, H. K. Kwan	Power-oriented delay budgeting for combinational circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Chunhong Chen, Jiang Zhao, Majid Ahmadi	A Novel State Encoding Algorithm for Low Power Implementation.	Journal of Circuits, Systems, and Computers	2005	DBLP DOI BibTeX RDF
1	Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh	Timing driven gate duplication.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min	Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems.	ISLPED	2004	DBLP DOI BibTeX RDF	anti-collision protocols, low power, radio-frequency identification
1	Chunhong Chen, Jiang Zhao, Majid Ahmadi	A semi-Gray encoding algorithm for low-power state assignment.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh	Budget Management with Applications.	Algorithmica	2002	DBLP DOI BibTeX RDF
1	Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh	Predicting potential performance for digital circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Chunhong Chen, Jiang Zhao, Majid Ahmadi	Probability-based approach to rectilinear Steiner tree problems.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Chunhong Chen, Changjun Kang, Majid Sarrafzadeh	Activity-sensitive clock tree construction for low power.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, clock gating, clock tree, activity pattern
1	Chunhong Chen	Physical design with multiple on-chip voltages.	ISPD	2002	DBLP DOI BibTeX RDF
1	Chunhong Chen	Probabilistic Analysis of Rectilinear Steiner Trees.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Chunhong Chen, Majid Sarrafzadeh	Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis.	DATE	2002	DBLP DOI BibTeX RDF
1	Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh	Activity-driven clock design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh	On gate level power optimization using dual-supply voltages.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh	Timing driven gate duplication in technology independent phase.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Chunhong Chen, Majid Sarrafzadeh	Power reduction by simultaneous voltage scaling and gate sizing.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh	Potential Slack: An Effective Metric of Combinational Circuit Performance.	ICCAD	2000	DBLP BibTeX RDF
1	Chunhong Chen, Majid Sarrafzadeh	Provably good algorithm for low power consumption with dual supply voltages.	ICCAD	1999	DBLP BibTeX RDF
1	Chunhong Chen, Majid Sarrafzadeh	An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages.	ICCD	1999	DBLP DOI BibTeX RDF	Two-voltage, Algorithm, Low power, Gate-level

Publications of "Chunhong Chen" ( http://dblp.L3S.de/Authors/Chunhong_Chen )