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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 8 publication records. Showing 8 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chunhua Yao, Kewal K. Saluja, Parmesh Ramanathan |
Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Krishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja |
A low cost approach to calibrate on-chip thermal sensors. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Temperature Dependent Test Scheduling for Multi-core System-on-Chip. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Thermal-Aware Test Scheduling Using On-chip Temperature Sensors. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Power and thermal constrained test scheduling. |
ITC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. |
Asian Test Symposium |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar |
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
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