Search results for "Ciaran Toal"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kieran McLaughlin, Dwayne Burns, Ciaran Toal, Colm McKillen, Sakir Sezer	Fully hardware based WFQ architecture for high-speed QoS packet scheduling.	Integration	2012	DBLP DOI BibTeX RDF
1	Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Xin Yang	Design and Implementation of a Field Programmable CRC Circuit Architecture.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic	An FPGA Based Memory Efficient Shared Buffer Implementation.	FPL	2007	DBLP DOI BibTeX RDF
1	Motasem Abdelghani, Sakir Sezer, Emi Garcia, Jun Mu, Ciaran Toal	FPGA-Based Lookup Circuit for Session-Based IP Packet Classification.	AHS	2007	DBLP DOI BibTeX RDF
1	Ciaran Toal, Dwayne Burns, Kieran McLaughlin, Sakir Sezer, Stephen O'Kane	An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing.	AHS	2007	DBLP DOI BibTeX RDF
1	Ciaran Toal, Sakir Sezer, Xin Yang, Kieran McLaughlin, Dwayne Burns, Tiberiu Seceleanu	Programmable CRC circuit architecture.	SoCC	2007	DBLP DOI BibTeX RDF
1	Ciaran Toal, Sakir Sezer, Xin Yang	A VLSI GFP Frame Delineation Circuit.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Ciaran Toal, Sakir Sezer	Investigation into programmability for layer 2 protocol frame delineation architectures.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Ciaran Toal, Sakir Sezer	A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA.	AICT/SAPIR/ELETE	2005	DBLP DOI BibTeX RDF	reg
1	Sakir Sezer, Ciaran Toal, Emi Garcia, V. Stewart	A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling.	IPDPS	2004	DBLP DOI BibTeX RDF	reconfigurable packet scheduling, SCFQ, Reconfigurable architectures, WFQ, network processing
1	Ciaran Toal, Sakir Sezer	The Implementation of Scalable ATM Frame Delineation Circuits.	ICT	2004	DBLP DOI BibTeX RDF
1	Emi Garcia-Palacios, Sakir Sezer, Ciaran Toal, Stephen Dawson	Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access.	ICT	2004	DBLP DOI BibTeX RDF
1	Brendan McAllister, Sakir Sezer, Ciaran Toal	Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler.	FPL	2003	DBLP DOI BibTeX RDF
1	Ciaran Toal, Sakir Sezer	A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET.	IPDPS	2003	DBLP DOI BibTeX RDF
1	Ciaran Toal, Sakir Sezer, Xing Yu	A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. (PDF / PS)	FCCM	2003	DBLP DOI BibTeX RDF
1	Ciaran Toal, Sakir Sezer	A 32-Bit SoPC Implementation of a P5.	ISCC	2003	DBLP DOI BibTeX RDF

Publications of "Ciaran Toal" ( http://dblp.L3S.de/Authors/Ciaran_Toal )