Search results for "Circuit design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Goutam Debnath, K. Debnath, R. Fernando	The Pentium processor-90/100, microarchitecture and low power circuit design.	VLSI Design	1995	DBLP DOI BibTeX RDF	BIMOS integrated circuits, Pentium processor-90/100, low power circuit design, BiNMOS process, power consumption reduction, symmetric dual processing feature, multithreaded operating systems, 0.6 micron, 3.3 V, computer architecture, microarchitecture, integrated circuit design, microprocessor chips, 100 MHz
3	Hai-qin Xu, Yong-sheng Ding, Zhi-hua Hu	Adaptive immune genetic algorithm for logic circuit design.	GEC Summit	2009	DBLP DOI BibTeX RDF	evolutionary design of circuits, logic circuit design, genetic algorithm, evolvable hardware, immune genetic algorithm
3	Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu	An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node.	ISQED	2008	DBLP DOI BibTeX RDF	Asynchronous Circuit Design, Single Track, Dual-Rail, Fast Forwarding
3	Radomir S. Stankovic, Rolf Drechsler	Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	Kronecker, MVL, decision diagrams, circuit design
3	Imtiaz P. Shaik, Michael L. Bushnell	Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .	VTS	1995	DBLP DOI BibTeX RDF	low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions
3	L. F. Fuller, C. Kraaijenvanger	Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education
2	Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz	Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis.	ISCA	2010	DBLP DOI BibTeX RDF	co-optimization, design trade-offs, optimization, energy efficiency, design space exploration, microarchitecture
2	Amlan Ghosh, Rob Franklin, Richard B. Brown	Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation.	VLSI Design	2010	DBLP DOI BibTeX RDF	analog circuit design methodologies, input switching, NBTI, body biasing
2	Kevin Zhang	Circuit design in nano-scale CMOS era: opportunities & challenges.	ISLPED	2009	DBLP DOI BibTeX RDF	VLSI, CMOS, circuit
2	Gabriel Oltean, Sorin Hintea, Emilia Sipos	A Genetic Algorithm-Based Multiobjective Optimization for Analog Circuit Design.	KES	2009	DBLP DOI BibTeX RDF	Pareto ranking, genetic algorithm, multiobjective optimization, Pareto front, analog circuit design
2	Eduardo José Solteiro Pires, Luís Mendes, Paulo B. de Moura Oliveira, José António Tenreiro Machado, Nuno M. Fonseca Ferreira, João Caldinhas Vaz, Maria J. Rosário	Single-objective front optimization: application to rf circuit design.	GECCO	2008	DBLP DOI BibTeX RDF	radio frequency circuit design, single-objective front, multi-objective evolutionary algorithm
2	Zhihua Wang, Songping Mai, Chun Zhang	Power Issues on Circuit Design for Cochlear Implants.	DELTA	2008	DBLP DOI BibTeX RDF	low power, power efficiency, cochlear implant
2	Suganth Paul, Rajesh Garg, Sunil P. Khatri	Pipelined network of PLA based circuit design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	synchronous, pipelining, PLA
2	Paul Tarau, Brenda Luderman	Exact combinational logic synthesis and non-standard circuit design.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	asymmetrical logic operators, exact combinational circuit synthesis, minimal transistor-count circuits, minimal universal boolean logic libraries
2	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann	Sizing Rules for Bipolar Analog Circuit Design.	DATE	2008	DBLP DOI BibTeX RDF
2	Che-Wei Lin, Jeen-Shing Wang	A digital circuit design of hyperbolic tangent sigmoid function for neural networks.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Ad M. G. Peeters, Mark de Wit	Asynchronous circuit design using Handshake Solutions.	SoCC	2008	DBLP DOI BibTeX RDF
2	Saravanan Ramamoorthy, Haibo Wang, Sarma B. K. Vrudhula	A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design.	ISQED	2008	DBLP DOI BibTeX RDF	low power, memory, circuit design, FIFO
2	Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia	Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF	Diode-resistor logic, logic-level degradation, nano-crossbar circuit, robust circuit design
2	Zhai Zhang, Youren Wang, Shanshan Yang, Rui Yao, Jiang Cui	The research of self-repairing digital circuit based on embryonic cellular array.	Neural Computing and Applications	2008	DBLP DOI BibTeX RDF	Self-repairing digital circuit, Embryonic cellular array, Fault-tolerance design, Digital circuit design
2	Jens Petter Abrahamsen, Tor Sverre Lande	Soft-well digital circuit design.	SBCCI	2007	DBLP DOI BibTeX RDF	well biasing, reliability, low power design
2	Kunhyuk Kang, Keejong Kim, Kaushik Roy	Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.	DAC	2007	DBLP DOI BibTeX RDF
2	Dongwon Seo, Yuhua Guo, Manu Mishra	High-Voltage Analog Circuit Design using Thin-Oxide MOS Devices only.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Saihua Lin, Huazhong Yang, Rong Luo	A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Huifei Rao, Jie Chen 0002, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao	Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Humberto Campanella, Arantxa Uranga, Pascal Nouet, Pedro De Paco, Nuria Barniol, Jaume Esteve	Instantaneous de-embedding of the on-wafer equivalent-circuit parameters of acoustic resonator (FBAR) for integrated circuit applications.	SBCCI	2007	DBLP DOI BibTeX RDF	RF circuit design, parameter extraction and fitting, thin-film bulk acoustic wave resonators (FBAR), MEMS
2	Xudong Niu, Yan Song, Bo Li, Wei Bian, Yadong Tao, Feng Liu, Jinhua Hu, Yu Chen, Frank He	Tests on Symmetry and Continuity between BSIM4 and BSIM5.	ISQED	2007	DBLP DOI BibTeX RDF	BSIM4, BSIM5, CMOS circuit design, symmetry, continuity, compact model
2	Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri	A PLA based asynchronous micropipelining approach for subthreshold circuit design.	DAC	2006	DBLP DOI BibTeX RDF	micro-pipelining, asynchronous, PLA, sub-threshold
2	Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu	A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, Andreas Ripp	DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.	DATE	2006	DBLP DOI BibTeX RDF
2	Oktay Altun, Mark F. Bocko	Robust analog circuit design: a set theoretic approach.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Doina Logofatu, Rolf Drechsler	Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion.	EvoWorkshops	2006	DBLP DOI BibTeX RDF	Data Ordering Problem, Transition Minimization, Optimization, Complexity, Low Power, Evolutionary Algorithms, Graph Theory, Digital Circuit Design
2	David W. Parent, Eric J. Basham, Shao Ng, Paul B. Weil	An Analog Leaf Cell for Analog Circuit Design.	MSE	2005	DBLP DOI BibTeX RDF
2	Jihyun Lee, Yong-Bin Kim	ASLIC: A Low Power CMOS Analog Circuit Design Automation.	ISQED	2005	DBLP DOI BibTeX RDF
2	Cecília Reis, José António Tenreiro Machado, J. Boaventura Cunha	Fractional dynamic fitness functions for GA-based circuit design.	GECCO	2005	DBLP DOI BibTeX RDF	fractional calculus, logic circuit design, genetic algorithms
2	Angelo Marcello Anile, Vincenzo Cutello, Giuseppe Nicosia, Rosario Rascunà, Salvatore Spinella	Comparison among evolutionary algorithms and classical optimization methods for circuit design problems.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
2	Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich	Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?	DATE	2005	DBLP DOI BibTeX RDF
2	Chien-Cheng Tseng, Tsung-Ming Hwang	Quantum circuit design of discrete Hartley transform using recursive decomposition formula.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Chien-Cheng Tseng, Tsung-Ming Hwang	Quantum circuit design of 8×8 discrete cosine transform using its fast computation flow graph.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Rouying Zhan, Haigang Feng, Qiong Wu, Xiaokang Guan, Guang Chen, Haolu Xie, Albert Z. Wang	Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Wendan Xu, Donglai Xu, Ian French	An Improved Band-Gap Voltage Reference Circuit Design for Multimedia VLSI Systems Integration Applications.	HSNMC	2004	DBLP DOI BibTeX RDF
2	A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky	A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations.	IOLTS	2004	DBLP DOI BibTeX RDF
2	Yang Zhang, Stephen L. Smith, Andy M. Tyrrell	Digital Circuit Design using Intrinsic Evolvable Hardware.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	Jintae Kim, Jaeseo Lee, Lieven Vandenberghe	Techniques for improving the accuracy of geometric-programming based analog circuit design optimization.	ICCAD	2004	DBLP DOI BibTeX RDF
2	Fengming Zhang, Rui Tang, Yong-Bin Kim	SET-based nano-circuit simulation and design method using HSPICE.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	SET circuit design, SET modeling, SET simulation with HSPICE
2	Christian Lang, Bernd Steinbach	Bi-Decomposition of Function Sets in Multiple-Valued Logic for Circuit Design and Data Mining.	Artif. Intell. Rev.	2003	DBLP DOI BibTeX RDF	bi-decomposition, differential calculus, multi-level circuit design, data mining, machine learning, logic synthesis, multiple-valued logic
2	Woo Jin Kim, Yong-Bin Kim	Automating Wave-Pipelined Circuit Design.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
2	Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio	An Analog Integrated Circuit Design Laboratory.	MSE	2003	DBLP DOI BibTeX RDF
2	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design.	ISVLSI	2003	DBLP DOI BibTeX RDF
2	Ammar Aljer, Philippe Devienne, Sophie Tison, Jean-Louis Boulanger, Georges Mariano	BHDL: Circuit Design in B.	ACSD	2003	DBLP DOI BibTeX RDF
2	Karen O. Egiazarian, Jaakko Astola, Radomir S. Stankovic, Milena Stankovic	Circuit design from optimal wavelet packet series expressions.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Lyudmila Zinchenko, Heinz Mühlenbein, Victor Kureichik, Thilo Mahnig	A Comparison of Different Circuit Representations for Evolutionary Analog Circuit Design.	ICES	2003	DBLP DOI BibTeX RDF
2	Gunnar Tufte, Pauline C. Haddow	Building Knowledge into Developmental Rules for Circuit Design.	ICES	2003	DBLP DOI BibTeX RDF
2	Guy G. Lemieux, David M. Lewis	Circuit design of routing switches.	FPGA	2002	DBLP DOI BibTeX RDF
2	F. A. Samman, R. S. Sadjad	Analog MOS circuit design for reconfigurable fuzzy logic controller.	APCCAS	2002	DBLP DOI BibTeX RDF
2	Wei Sun, Richard M. M. Chen, Yao-Lin Jiang	Tolerance analysis for electronic circuit design using the method of moments.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Edoardo Charbon, Ilhami Torunoglu	Watermarking Techniques for Electronic Circuit Design.	IWDW	2002	DBLP DOI BibTeX RDF
2	Lyudmila Zinchenko, Heinz Mühlenbein, Victor Kureichik, Thilo Mahnig	Application of the Univariate Marginal Distribution Algorithm to Analog Circuit Design.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
2	Kevin T. Kornegay	Anatomy of a Radio Frequency Integrated Circuit Design Course. (PDF / PS)	MSE	2001	DBLP DOI BibTeX RDF
2	Mark Schlarmann, Randall L. Geiger	Prototype implementation of a WWW based analog circuit design tool.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Nikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev	Semi-modular Latch Chains for Asynchronous Circuit Design.	PATMOS	2000	DBLP DOI BibTeX RDF
2	Gi-Noung Byun, Chol-U Lee, Seung-Yong Park, Heung-Soo Kim	A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix Equation. (PDF / PS)	ISMVL	2000	DBLP DOI BibTeX RDF
2	Thomas D. Burd, Robert W. Brodersen	Design issues for dynamic voltage scaling.	ISLPED	2000	DBLP DOI BibTeX RDF	variable voltage, energy efficient, processor, circuit design
2	Fabian Vargas, Alexandre M. Amory	Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	transient-fault tolerant VHDL descriptions, area overhead analysis, reliable complex circuit design, harmful environments, reliability level, early-estimation, maximum area overhead, redundancy insertion, application minimum reliability requirement, FT-PRO tool, fault tolerant computing, redundancy, microprocessor, integrated circuit design, circuit CAD, CAD tool, transients, reliability estimation, memory elements, integrated circuit reliability, fault-tolerant circuit
2	P. Chow, Soon Ong Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja	The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
2	Gérard Berry	Esterel and Jazz: Two Synchronous Languages for Circuit Design (Abstract).	CHARME	1999	DBLP DOI BibTeX RDF
2	S. Kimura, T. Otsuji, H. Kikuchi, K. Murata, E. Sano	Circuit design technologies for high-speed lightwave communications beyond 40 Gbit/s.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González	Circuit Design using Resonant Tunneling Diodes.	VLSI Design	1998	DBLP DOI BibTeX RDF	Quantum device, Pipelining, Multiple-Valued Logic, Nanoelectronics, Resonant Tunneling Diode
2	Paul F. Stelling, Vojin G. Oklobdzija	Implementing Multiply-Accumulate Operation in Multiplication Time.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	multiply-accumulate operation, multiplication time, optimal delays, instruction time, optimal multiply-accumulate circuit, RISC CPU, partial product reduction tree, final adder, digital signal processing, power savings, multiplying circuits, circuit design, VLSI circuits, parallel multiplier, processor performance, video applications, graphics applications, clock speed
2	A. Jee, F. Joel Ferguson	A methodolgy for characterizing cell testability.	VTS	1997	DBLP DOI BibTeX RDF	cell testability, stuck-at fault coverage, IC quality, physical design for testability, metric, integrated circuit design, integrated circuit design, DPM, manufacturing defects
2	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
2	Anantha Chandrakasan	Ultra low power digital signal processing.	VLSI Design	1996	DBLP DOI BibTeX RDF	ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
2	Robert B. Norwood, Edward J. McCluskey	Synthesis-for-scan and scan chain ordering.	VTS	1996	DBLP DOI BibTeX RDF	synthesis-for-scan procedure, scan chain ordering, testable circuit design, beneficial scan, VLSI, logic testing, integrated circuit testing, design for testability, logic design, sequential circuits, logic synthesis, flip-flops, integrated circuit design, integrated logic circuits, test strategy, boundary scan testing, functional specifications
2	Fadi Y. Busaba, Parag K. Lala	A graph coloring based approach for self-checking logic circuit design.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	logic circuit design, bidirectional error, residue weights assignments, output lines, errors identification, graph theory, logic testing, integrated circuit testing, logic design, error detection, error detection, automatic testing, graph coloring, fault location, integrated logic circuits, graph colouring, self-checking, residue codes, single stuck-at fault
2	Steven Parkes, Prithviraj Banerjee, Janak H. Patel	A parallel algorithm for fault simulation based on PROOFS . (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	fault partitioning, dynamic partitioning schemes, compute intensive task, integrated circuit design process, rapid design turn around, ProperPROOFS, parallel extension, PROOFS fault simulation package, distributed method, fault redistribution, ISCAS-89 benchmark set, high performance serial fault simulation applications, parallel algorithms, parallel algorithm, parallel architectures, parallel architectures, fault diagnosis, logic testing, sequential circuits, sequential circuits, circuit analysis computing, logic partitioning
2	Robert Spence, Lisa Tweedie, Huw Dawkes, Hua Su	Visualization for functional design.	INFOVIS	1995	DBLP DOI BibTeX RDF	visualisation tools, Influence Explorer, Prosection Matrix, engineering artifact design, electronic circuit design, user interfaces, CAD, optimisation, interactive systems, data visualisation, circuit CAD, interactive display, manufacturing process, engineering graphics, functional design
2	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
2	Trevor J. Smedley	A High-Level Visual Language for the Graphical Description of Digital Circuits. (PDF / PS)	VL	1995	DBLP DOI BibTeX RDF	pulse circuits, high-level visual language, graphical description, programming language systems, digital design systems, full-featured visual programming language, complex circuit specification, repetitive structures, conditional structures, visual languages, circuit analysis computing, circuit CAD, digital circuits, engineering graphics, program structures, digital circuit design
2	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
2	Joe Rodriguez-Tellez, Kahtan A. Mezher, M. Al-Daas	Computationally efficient and accurate capacitance model for the GaAs MESFET for microwave nonlinear circuit design.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Paul B. Jackson	Nuprl and Its Use in Circuit Design.	TPCD	1992	DBLP BibTeX RDF
2	Jung-Gen Wu	Automatic knowledge acquisition in a digital circuit design system.	EURO-DAC	1990	DBLP DOI BibTeX RDF
2	Min-You Wu, Ibrahim N. Hajj	Switching network logic approach to sequential MOS circuit design.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	V. Sundarapandian, Ihsan Pehlivan	Analysis, control, synchronization, and circuit design of a novel chaotic system.	Mathematical and Computer Modelling	2012	DBLP DOI BibTeX RDF
1	Qinghong Bu, Ning Li, Kenichi Okada, Akira Matsuzawa	Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Jung-Lin Yang, Shin-Nung Lu, Pei-Hsuan Yu	Asynchronous Circuit Design on Field Programmable Gate Array Devices.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Shao-Chang Huang, Ke-Horng Chen, Wei-Yao Lin, Zon-Lon Lee, Kun-Wei Chang, Erica Hsu, Wenson Lee, Lin-Fwu Chen, Chris Lu	Embedded I/O PAD Circuit Design for OTP Memory Power-Switch Functionality.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler	RevKit: A Toolkit for Reversible Circuit Design.	Multiple-Valued Logic and Soft Computing	2012	DBLP BibTeX RDF
1	Jaeyoon Kim, Paul Michael Solomon, Sandip Tiwari	Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Massimo Alioto	Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero	Circuit design of a dual-versioning L1 data cache.	Integration	2012	DBLP DOI BibTeX RDF
1	Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy	A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Ken Takeuchi, Jan Crols, Kevin Zhang, Mike Clinton, Tadaaki Yamauchi	Robust VLSI circuit design & systems for sustainable society.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Javier de San Pedro, Josep Carmona, Jordi Cortadella, Jordi Petit	Integrating formal verification in an online judge for e-Learning logic circuit design.	SIGCSE	2012	DBLP DOI BibTeX RDF
1	Linh Hunyh, Ilias Tagkopoulos	A robust, library-based, optimization-driven method for automatic gene circuit design.	ICCABS	2012	DBLP DOI BibTeX RDF
1	Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa	Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Norio Sadachika, Shu Mimura, Akihiro Yumisaki, Koh Johguchi, Akihiro Kaya, Mitiko Miura-Mattausch, Hans Jürgen Mattausch	Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kyoya Takano, Ryuichi Fujimoto, Kosuke Katayama, Mizuki Motoyoshi, Minoru Fujishima	Analysis of De-Embedding Error Cancellation in Cascade Circuit Design.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kwang-Jow Gan, Cher-Shiung Tsai, Yu-Kuang Li, Jenq-Jong Lu	Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee	The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF